Marnix Tack

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

On the impact of carbon-doping on the dynamic Ron and off-state leakage current of 650V GaN power devices

A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.

UltiMOS: A local charge-balanced trench-based 600V super-junction device

This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with V<inf>bd</inf>=730V and a Ron=23 mΩ.cm² are demonstrated.

AlGaN/GaN power device technology for high current (100+ A) and high voltage (1.2 kV)

This paper extends our 650V rated GaN device technology to current ratings in excess of 100A. For the first time, devices with single digit Ron values are reported. A record low value of 6mΩ is measured at 100A. The device technology is shown to be fully current collapse free, over the complete voltage and temperature window. Intrinsic reliability test data up to Vds=900V, and T=200°C is provided. In addition, by using a thicker GaN buffer, 20A rated GaN power devices up to 1.2kV are presented, with leakage current ~100nA. This is a first step to allow AlGaN/GaN power devices to compete with Si IGBTs and SiC MOSFETs.

Solutions to improve flatness of Id-Vd curves of rugged nLDMOS

This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.

New methodology on electro-thermal characterization and modeling of large power drivers using lateral PNP BJTs

This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using lateral bipolars. Maximum elevation of junction temperature due to the electrical power stress is sensed in the field of the drivers. Those measurements are further complemented by the transient interferometric mapping (TIM) inspection. For the first time a data driven segmented electro-thermal model is proposed to describe accurately the non-uniform current density and the thermal profile behavior of a large power driver.

A New Method to Improve Tradeoff Performance for Advanced Power MOSFETs

In this letter, a new way of operating a split-gate vertical LOCOS MOSFET based on the depletion of the drift region by MOS capacitors is proposed. By using auxiliary bias on the split-gate electrode of the device, optimum drift-region charge can be increased to reduce its specific on-resistance. Theoretical investigation reveals that nearly 25% reduction in the on-state resistance can be achieved. If an additional bias is used on the split-gate electrode during on-state, a further improvement can be observed.

Novel 3D electro-thermal robustness optimization approach of super junction power MOSFETs under unclamped inductive switching

This paper presents a novel approach to optimize the electro-thermal robustness of a super-junction power MOSFET under unclamped inductive switching (UIS) conditions. The loosely coupled electro-thermal simulation has been used to predict accurately the interaction between the core active device and the termination rings. The simulation results have been validated by the emission microscopy (EMMI) measurements and the transient IR thermography photos.

Energy limits for unclamped inductive switching in high-voltage planar and SuperJunction power MOSFETs

In this work the maximum UIS energy capability (Eas) for High-Voltage (600V-900V) Planar and SuperJunction (SJ) power MOSFETs is analyzed through experiment, TCAD simulation and analytical modeling. A new theoretical approach considering a buried heat source is presented to accurately predict Eas values in a wide range of voltage capability and load inductor values.

Floating gate AC nulling (FGAN) technique for characterisation of matching properties of MOS capacitors

This paper presents a floating gate AC nulling technique for the characterisation and modelling of the matching properties of MOS capacitors. The technique is insensitive to the parasitic capacitor and charge accumulation on the floating gate, due to AC nulling. It is accurate, robust and easily used.