Martin G. Buehler

An Experimental Study of Various Cross Sheet Resistor Test Structures

Newly designed cross sheet resistors are shown to give the same (within 0.5%) measured sheet resistance as conventional van der Pauw structures. Diffused boron and phosphorus layers with sheet resistances near 200 Ω/ were studied with the sampled areas varying from a square 6.4 μm (0.25 mil) on a side to a circle 762 μm (30.0 mils) in diameter. An increase in measured sheet resistance values was observed due to surface leakage currents, and an equivalent circuit model was developed to explain the results. The effect of joule heating on measured sheet resistance values was observed in both large and small cross structures.

A numerical analysis of various cross sheet resistor test structures

Abstract Various four-terminal cross sheet resistor test structures were analyzed to determine the effect of the contact arm width and length on the measured sheet resistance. A nine-point finite difference approximation to the Laplace equation was used with a six-resistor equivalent circuit to solve for the sheet resistance measurement error. The error indicates the difference between the true sheet resistance and the sheet resistance calculated from the van der Pauw formula. The analysis demonstrates that many novel designs are possible. In particular, the Greek-cross sheet resistor is a valid van der Pauw test structure if the arm length is greater than the arm width. This test structure is important in that it allows the accurate measurement of the sheet resistance of a very small region whose width is limited only by the fabrication technology.

A study of the gold acceptor in a silicon p+n junction and an n-type MOS capacitor by thermally stimulated current and capacitance measurements☆

Abstract The thermally stimulated current and capacitance responses of a gold doped p+n junction and n-type MOS capacitor were measured experimentally and modeled theoretically for the case of majority-carrier defect charging. The gold acceptor atoms are initially charged with electrons at low temperatures, and during the heating cycle, excess electrons are released from the gold atoms. The thermally stimulated current response for this phase is similar in both structures and has a distinctive peak-and-valley shape and an emission temperature about 220 K. During the steady-state phase, a current peak occurs in the MOS capacitance response. A physical model was developed and the influence of various parameters on the current and capacitance measurements was quantified. Various analytical schemes are described which allow rapid identification of the gold defect center and rapid computation of its density. A simple and inexpensive apparatus is described which is capable of heating rates as high as 10 K/s.

Measurement of the resistivity of a thin square sample with a square four-probe array

Abstract Geometrical correction factors are evaluated for the measurement of the resistivity of a square conducting sample whose thickness is small compared to the probe spacing of a square four-probe array. The correction factors allow the computation of the resistivity when the probes are not on the periphery of the square sample. The solution is based on the method of images and is written in a compact, easily-evaluated form. The resistivity measurement error encountered with the square sample is presented in graphical form for use in test structure design.

A planar four-probe test structure for measuring bulk resistivity

A small planar four-probe test structure for measuring the bulk or collector resistivity of silicon wafers was designed and fabricated with a bipolar transistor process. Analogous to a mechanical square array four-point probe, the planar four-probe structure consists of a large-area base diffusion which is broken at four points through which contact is made to the undiffused collector material. A probe spacing of 2.25 mil (57.2 µm) allows the resistivity of the silicon wafer to be measured with good spatial resolution. A correction factor was derived to obtain the true resistivity from measurements on a wafer with finite thickness and a conducting backside, and it is presented along with the correction factors for other cases. The test device was fabricated in silicon wafers whose resistivities ranged from 0.013 Ω. cm to 12 Ω. cm in n-type material and from 0.7 Ω. cm to 30 Ω. cm in p-type material. Planar four-probe resistivity values are compared with mechanical four-probe values taken on the same wafers before fabrication, and the results are generally in agreement within ±3 percent.

Peripheral and diffused layer effects on doping profiles

The impurity profile of an epitaxial layer has been determined from the capacitance-voltage ( C-V ) characteristics of a diffused p-n junction. The C-V characteristics were corrected for peripheral and diffused layer effects. Peripheral capacitance corrections account for the lateral spread of the space-charge region, whose periphery is assumed to be cylindrical. Diffused layer corrections account for the penetration of the space-charge region into the diffused layer, assumed to be Gaussian. The importance of these corrections can be estimated from graphs that cover a wide range of practical diffusion conditions and junction diameters. The sensitivity of profiles to the assumed Gaussian diffusion are examined. Finally, the corrections are applied to an experimental junction and the results are presented from a computer printout. The Appendix includes graphs for determining the space-charge width of a Gaussian-diffused silicon junction, given the diffused layer sheet resistance, junction depth, and background concentration.

Effect of the drain—Source voltage on dopant profiles obtained from the DC MOSFET profile method

An analysis was developed for the influence of a finite drain-source voltage, VDS, on dopant profiles derived from the dc MOSFET profile method. It indicates that the measured profile of uniformly doped material falls below the true profile near the surface. The effect occurs because the edge of the depletion region in the silicon is not parallel to the oxide-silicon interface for a finite VDS. For the case of uniformly doped silicon near room temperature, the analysis indicates, for reverse bias applied across the silicon, that the error in the measured dopant density due to a finite VDSis less than 1 percent ifV_{DS} \leq 0.5of file built-in voltage, a condition that is easily met in practice. The analysis also reveals that the profile depth determined from the depth-profile equation is a simple average of the depletion widths at the source and drain ends of the channel in uniformly doped silicon. Experimental results are presented which confirm the general trends indicated by the analysis.