Martin Holzer

Slot-wise maximum likelihood estimation of the tag population size in FSA protocols

Framed Slotted Aloha (FSA) is a popular anticollision technique in state-of-the-art RF-ID systems, as in ISO/IEC CD 18000-6 for 900MHz or the EPCglobal HF Gen 2 draft for 13.56MHz. In many applications the number of tags entering and leaving the detection range of the reader is subject to a strong fluctuation and usually unknown. The current number of tags in the field is a crucial parameter to operate the FSA anti-collision in an optimal manner. Therefore, a lot of effort is spent on the estimation of this parameter and a range of different estimation techniques exist. The contributions of this paper are: 1) a closed formula for the probability of any observed event defined by the number of empty, singleton, and collision slots in the observed frame is developed and empirically verified. 2) This formula is then modified to compute the probability for partly observed frames as well which is of great interest as the referred standards allow for the in-frame adjustment of the frame size without quitting the interrogation round. 3) Then, a maximum likelihood estimator is formulated to yield the estimated number of tags on a slot-wise basis. 4) Its superior estimation performance is compared to the known best estimators over the complete parameter set. While its performance is strongly superior compared to Schoute¿s estimate, compared to Vogt¿s MSE estimator only marginally improvement is obtained1.

Design Space Exploration with Evolutionary Multi-Objective Optimisation

High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high level synthesis are two-fold. At first the level of abstraction is raised and secondly this allows for exploring the design space to a higher degree than on register transfer level. The design space can be explored by applying several kinds of source code transformations like loop unrolling and tree height reduction. Performing design space exploration manually leads to inefficient and inflexible mappings. This work describes the automated design space exploration for area timing trade-offs by utilising evolutionary multi-objective optimisation. Several performance improvements for genetic algorithms are introduced, which target a fast and accurate design space exploration. Finally, the performance of the proposed algorithm is evaluated.

A consistent design methodology for wireless embedded systems

Complexity demand of modern communication systems, particularly in the wireless domain, grows at an astounding rate, a rate so high that the available complexity and even worse the design productivity required to convert algorithms into silicon are left far behind. This effect is commonly referred to as the design productivity crisis or simply the design gap. Since the design gap is predicted to widen every year, it is of utmost importance to look closer at the design flow of such communication systems in order to find improvements. While various ideas for speeding up designs have been proposed, very few have found their path into existing EDA products. This paper presents requirements for such tools and shows how an open design environment offers a solution to integrate existing EDA tools, allowing for a consistent design flow, considerably speeding up design times.

Static code analysis of functional descriptions in SystemC

The co-design of hardware and software systems with object oriented design languages like SystemC has become very popular Static analysis of those descriptions allows to conduct the design process with metrics regarding quality of the code as well as with estimations of the properties of the final design. This paper shows the utilization of software metrics and the computation of high level metrics for SystemC, whose generation is embedded into a complete design methodology. The performance of this analysis process is demonstrated on a UMTS cell searching unit

Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips

Early performance estimation of a system-on-chip design is a key issue for a successful design methodology. One of the most important parameters is the run time of a function. Especially optimization techniques like hw/sw partitioning rely on those estimations. This paper presents a static analysis method in order to characterize a hardware acceleration unit regarding its run time. The performance of the presented method is shown on several examples from the embedded systems area and compared to results from high level synthesis.

Efficient design methods for embedded communication systems

Nowadays, design of embedded systems is confronted with complex signal processing algorithms and a multitude of computational intensive multimedia applications, while time to product launch has been extremely reduced. Especially in the wireless domain, those challenges are stacked with tough requirements on power consumption and chip size. Unfortunately, design productivity did not undergo a similar progression, and therefore fails to cope with the heterogeneity of modern architectures. Electronic design automation tools exhibit deep gaps in the design flow like high-level characterization of algorithms, floating-point to fixed-point conversion, hardware/software partitioning, and virtual prototyping. This tutorial paper surveys several promising approaches to solve the widespread design problems in this field. An overview over consistent design methodologies that establish a framework for connecting the different design tasks is given. This is followed by a discussion of solutions for the integrated automation of specific design tasks.

Automatic generation of virtual prototypes

Virtual prototyping as an embedded system design technique has the potential to significantly increase efficiency of the design process. An environment for automatic generation of virtual prototypes (VPs) directly from algorithmic-level descriptions is presented here. It is implemented as part of a unified design methodology and produces VSIA compliant VPs. When applied to an industrial design flow of a UMTS receiver, this environment for automatic generation of VPs produced significant speedups over traditional manual VP creation, with savings in the order of hundreds to thousands of person-hours.

Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs

During recent years power optimisation has become one of the most challenging design goals in modern communication systems, particularly in the wireless domain. Many different approaches for task scheduling on single or multi-core systems exist, mostly addressing the minimisation of execution time or the number of processors used. The minimisation of the processors clock frequency by adjusting the supply voltage or directly by frequency scaling according to the chosen task scheduling has shown good results in the reduction of power consumption. Most of the known approaches base their core algorithms on graph representations for multi-rate systems or synchronous data flow (SDF) graphs, in a single frequency domain. In many cases a signal processing system comprises several frequency domains, in which processes have to be fired according to their in- and output data rates as well as to their frequency domain. In this work the superposition of frequency domains and data dependencies is incorporated into the optimisation process and used as a another degree of freedom. Several algorithms have been implemented and evaluated to minimise the required processors clock frequency, including a greedy, a simulated annealing, as well as a tabu search approach

A fully automated environment for verification of virtual prototypes

The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.

Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms

In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and time-to-market, the HW/SW partitioning problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with complex communication models, is intractable. Moreover most partitioning problems embed another NP-hard problem in its core: a huge number of valid schedules exist for a single partitioning solution. Powerful heuristics for the partitioning problem rely on list scheduling techniques to solve this scheduling problem. This paper is based on a rescheduling algorithm that performs better than popular list scheduling techniques and still preserves linear complexity by reusing former schedules. A sophisticated communication model is introduced and the rescheduling algorithm is modified to serve multi-core architectures with linear runtime.