Martin Lapisa

Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS

Wafer-level heterogeneous integration technologies for microoptoelectromechanical systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical systems (NEMS) enable the combination of dissimilar classes of materials and components into single systems. Thus, high-performance materials and subsystems can be combined in ways that would otherwise not be possible, and thereby forming complex and highly integrated micro- or nanosystems. Examples include the integration of high-performance optical, electrical or mechanical materials such as monocrystalline silicon, graphene or III-V materials with integrated electronic circuits. In this paper the state-of-the-art of wafer-level heterogeneous integration technologies suitable for MOEMS, MEMS, and NEMS devices are reviewed. Various heterogeneous MOEMS, MEMS, and NEMS devices that have been described in literature are presented.

One-Megapixel Monocrystalline-Silicon Micromirror Array on CMOS Driving Electronics Manufactured With Very Large-Scale Heterogeneous Integration

In this paper, we demonstrate the first high-resolution spatial-light-modulator chip with 1 million tilting micromirrors made of monocrystalline silicon on analog high-voltage complementary metal-oxide-semiconductor driving electronics. This device, as result of a feasibility study, shows good optical and excellent mechanical properties. The micromirrors exhibit excellent surface properties, with a surface roughness below 1-nm root mean square. Actuated micromirrors show no imprinting behavior and operate drift free. Very large-scale heterogeneous integration was used to fabricate the micromirror arrays. The detailed fabrication process is presented in this paper, together with a characterization of the SLM devices. Large arrays of individually controllable micromirrors are the enabling component in high-perfomance mask-writing systems and promising for high throughput deep-ultraviolet maskless lithography systems. The adoption of new materials with enhanced characteristics is critical in meeting the challenging demands with regard to surface quality and operation stability in the future. Very large-scale heterogeneous integration may enable virtually any solid-state material to be integrated together with CMOS electronics.

CMOS-Integrable Piston-Type Micro-Mirror Array for Adaptive Optics Made of Mono-Crystalline Silicon using 3-D Integration

This paper presents a novel CMOS-compatible fabrication process and evaluations of a micro mirror array (MMA) made of mono-crystalline silicon (m-Si) for adaptive optic (AO) applications. The m-Si mirror layer is transfer bonded from a silicon-on-insulator (SOI) donor wafer with adhesive wafer bonding towards an intermediate patterned polymer spacer layer and clamped with metal plating. We present a CMOS compatible, bond alignment-free fabrication scheme offering the potential for high air gap distances between substrate and mirrors and we show first measurements of the fabricated mirrors.

Drift-Free Micromirror Arrays Made of Monocrystalline Silicon for Adaptive Optics Applications

In this paper, we report on the heterogeneous integration of monocrystalline silicon membranes for the fabrication of large segmented micromirror arrays for adaptive optics applications. The design relies on a one-level architecture with mirrors and suspension formed within the same material, employing a large actuator gap height of up to 5.1 μm to allow for a piston-type mirror deflection of up to 1600 nm. Choosing monocrystalline silicon as actuator and mirror material, we demonstrate a completely drift-free operation capability. Furthermore, we investigate stress effects that degrade the mirror topography, and we show that the stress originates from the donor silicon-on-insulator wafer. The novel heterogeneous integration strategy used in this work is capable of reducing this stress to a large extent.

Room-temperature wafer-level hermetic sealing for liquid reservoirs by gold ring embossing

In this paper, we present a novel room temperature wafer-level sealing process for hermetic sealing of reservoirs filled with liquids. This technique can be used for e.g. drug delivery devices or thermo pneumatic devices. The sealing mechanism is based on plastic deformation of metal squeeze rings and embossing of target structures. Epoxy based underfill is used for mechanical stabilization of the wafer bond. We present experimental results from room-temperature bonding of glass wafers to silicon wafers with encapsulation of liquids in reservoirs.

Selective electroless nickel plating on oxygen-plasma-activated gold seed-layers for the fabrication of low contact resistance vias and microstructures

This paper presents a novel technique to selectively deposit nickel by electroless plating on gold seed layers using an oxygen-plasma-activation step. No prior wet surface pre-treatments or metal oxide etches are required. This enables the manufacturing of low-resistance vias for heterogeneous three-dimensional (3D) integration of MEMS but it is also a suitable technique for the fabrication of arbitrary shaped nickel-microstructures using chemically stable and cost-effective electroless nickel plating baths.

Fabrication of large-scale mono-crystalline silicon micro-mirror arrays using adhesive wafer transfer bonding

Today, spatial light modulators (SLMs) based on individually addressable micro-mirrors play an important role for use in DUV lithography and adaptive optics. Especially the mirror planarity and stability are important issues for these applications. Mono-crystalline silicon as mirror material offers a great possibility to combine the perfect surface with the good mechanical properties of the crystalline material. Nevertheless, the challenge is the integration of mono-crystalline silicon in a CMOS process with low temperature budget (below 450°C) and restricted material options. Thus, standard processes like epitaxial growth or re-crystallization of poly-silicon cannot be used. We will present a CMOS-compatible approach, using adhesive wafer transfer bonding with Benzocyclobutene (BCB) of a 300nm thin silicon membrane, located on a SOI-donor wafer. After the bond process, the SOI-donor wafer is grinded and spin etched to remove the handle silicon and the buried oxide layer, which results in a transfer of the mono-crystalline silicon membrane to the CMOS wafer. This technology is fully compatible for integration in a CMOS process, in order to fabricate SLMs, consisting of one million individually addressable mono-crystalline silicon micro-mirrors. The mirrors, presented here, have a size of 16×16 μm2. Deflection is achieved by applying a voltage between the mirrors and the underlying electrodes of the CMOS electronics. In this paper, we will present the fabrication process as well as first investigations of the mirror properties.

Hidden-hinge micro-mirror arrays made by heterogeneous integration of two mono-crystalline silicon layers

In this paper we present wafer-level heterogeneous integrated hidden-hinge micro-mirror arrays for adaptive optics applications. The micro-mirrors are made of mono-crystalline silicon and fabricated by two cycles of adhesive wafer bonding on fan-out substrates with addressing electrodes. The fabrication scheme allows the down-scaling of the micro-mirrors in size, the up-scaling of the array size and the implementation of additional material layers. Furthermore, large distances of the micro-mirrors to the electrodes can be achieved and hence a large deflection of the mirrors is possible. The micro-mirrors exhibit excellent deflection stability; no drift or hysteresis can be observed.

Very large scale heterogeneous system integration for 1-megapixel mono-crystalline silicon micro-mirror array on CMOS driving electronics

In this paper we demonstrate the first high mirror-count 1-level spatial light modulator (SLM) chip with 1 million tilting micro-mirrors made of mono-crystalline silicon on analogue, high-voltage CMOS driving electronics. The device from a feasibility study shows good optical and excellent mechanical properties. The micro-mirrors exhibit excellent surface properties with a surface roughness below 1 nm RMS, actuated micro-mirrors show no imprinting behavior and operate drift-free. Very large scale heterogeneous system integration was used to fabricate the micro-mirror array; the process is presented in this paper together with a characterization of the fabricated device.

Wafer-level heterogeneous 3D integration for MEMS and NEMS

In this paper the state-of-the-art in wafer-level heterogeneous 3D integration technologies for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) is reviewed. Various examples of commercial and experimental heterogeneous 3D integration processes for MEMS and NEMS devices are presented and discussed.