Martin Ostermayr

Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs

This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.

A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (Vth) and drain current (Id) distributions of p-MOS SRAM transistors pre and post NBTI Stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre and post NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the Static Noise Margin of a 6-T SRAM cell.

Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation

This paper presents Read Margin analysis for large SRAM arrays with a fast test method that even can be realized in dual-VDD product chips. Classical Static Noise Margin (SNM) is mostly suitable for single-cell simulation. Read Margin (RM) measurement allows analysis of large arrays and correlates to SNM, but requires a dedicated teststructure and long measurement time. The presented method analyzes the flipping of cells over varying supply voltage. The stability of large arrays can be characterized in read as well as in hold state depending on the state of the access transistors. Applying this method, the impact of Negative Bias Temperature Instability (NBTI) is demonstrated on both Read and Hold Margin in a 65 nm low power technology.

A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation

We present an area efficient test structure that allows a measurement of the statistical distribution of SRAM cell currents beyond 5 sigma variation. The test structure was fabricated in a 90 nm and a 65 nm CMOS technology. The measured data show that the device variations are Gaussian-distributed for more than 1 million devices, covering more than 5 sigma of variation. Monte Carlo simulations are used to validate the measurements.

Single exposure contacts are dead. Long live single exposure contacts

The paper describes a process/design co-optimization effort based on an SRAM design to enable a single exposure contact process for the 28nm technology half node. As a start, a change to the wiring concept of the standard SRAM design was implemented. The resulting individual contact layer elements may seem even more resolution critical to the casual observer. But in reality, the flexibility for source-mask optimization had been significantly improved. In a second step, wafer targets and mask dimension options (using various kinds of OPC methods and SRAF strategies) were run through several optimization iterations. This included interlevel considerations due to stringent overlap requirements. Several promising SRAM design as well as mask options were identified and experimentally verified to finally converge to an optimum mask and wafer target layout. Said optimum solution still supports an automated OPC approach using standard EDA tools and off the shelf OPC strategies. In a last step, a 1Mbit electrically testable SRAM was designed and manufactured together with alternative SRAM designs and process options. After explaining the changes to the wiring of the SRAM design, the paper discusses in great detail various mask optimization solutions and their consequences on wafer target and printability. Simulation and experimental results are compared and the concluding optimized solution is explained. Furthermore, some key lithography and etch process elements that became the single exposure process enabler are explained in more detail. Finally, the paper will take a look at electrical results of the 1Mbit electrically testable SRAM as the ultimate proof of concept.

Strategies for single patterning of contacts for 32nm and 28nm technology

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally novel design changes for single patterning along new capability in data preparation were both assessed to leverage minimal impact of implementation of a single patterning contact process into the existing 32nm and 28nm technology programs [1].

Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes

As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond J.-P. Han, T. Shimizu, L.-H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, A. Azuma, G. Yang, M. Eller, D. Jaeger, H. Zhuang, K. Miyashita, K. Stein, D. Nair, J.-H. Park, M. Hamaguchi, S. Kohler, D. Chanemougame, W. Li, K Kim, N. Kim, C. Wiedholz, S. Miyake, G. Tsutsui, H. van Meer, J. Liang, M. Ostermayr, J. Lian, M. Celik, R. Donaton, K. Barla, M.H. Na, Y. Goto, M. Sherony, F. Johnson, R. Wachnik, J. Sudijono,E. Kaste, R. Sampson, J.-H. Ku, A. Steegen, W. Neumueller Infineon Technologies, Renesas, IBM Microelectronics, STMicroelectronics, Toshiba America, GLOBALFOUNDRIES, Samsung Electronics, alliances at IBM SRDC, 2070 Rt 52, Hopewell Junction, NY12533; jh262@ieee.org,