Martin Palkovic

System-scenario-based design of dynamic embedded systems

In the past decade, real-time embedded systems have become much more complex due to the introduction of a lot of new functionality in one application, and due to running multiple applications concurrently. This increases the dynamic nature of todays applications and systems, and tightens the requirements for their constraints in terms of deadlines and energy consumption. State-of-the-art design methodologies try to cope with these novel issues by identifying several most used cases and dealing with them separately, reducing the newly introduced complexity. This article presents a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, which can be utilized by existing design methodologies to increase their efficiency. It is based on the concept of system scenarios, which group system behaviors that are similar from a multidimensional cost perspective—such as resource requirements, delay, and energy consumption—in such a way that the system can be configured to exploit this cost similarity. At design-time, these scenarios are individually optimized. Mechanisms for predicting the current scenario at run-time, and for switching between scenarios, are also derived. This design trajectory is augmented with a run-time calibration mechanism, which allows the system to learn on-the-fly during its execution, and to adapt itself to the current input stimuli, by extending the scenario set, changing the scenario definitions, and both the prediction and switching mechanisms. To show the generality of our methodology, we show how it has been applied on four very different real-life design problems. In all presented case studies, substantial energy reductions were obtained by exploiting scenarios.

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottle-neck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures

The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for many-core computing architectures.

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems

The ANTAREX project aims at expressing the application self-adaptivity through a Domain Specific Language (DSL) and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to Exascale. The DSL approach allows the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. We show through a mini-app extracted from one of the project application use cases some initial exploration of application precision tuning by means enabled by the DSL.

Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder

A cost-efficient realisation of an advanced multimedia system requires high-level memory optimisations to deal with the dominant memory cost. This typically results in more efficient code for both power and system bus load. However, significant performance improvement can also be achieved when carefully optimising the address functionality. This paper shows how the nature of this addressing code and the related control flow allows transformation of the complex index, iterator and condition expressions into efficient arithmetic. We apply our address optimisation (ADOPT) design technology to a low power memory optimised MPEG-4 decoder When mapped on popular programmable multimedia processor architectures, we obtain a factor of 2 in performance gain.

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach

The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. More in detail, the 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach

The main goal of the ANTAREX 1 project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management.

Parallel paradigms and run-time management techniques for many-core architectures: The 2PARMA approach

The 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. More in detail, the 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.

A flexible platform architecture for Gbps wireless communication

Reprogrammable radio platforms should not only offer flexibility and low power consumption but also conform to strict throughput and latency requirements mandated by the wireless standards. To achieve these challenging goals, we introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. We demonstrate three main achievements in running multiple wireless standards on our platform: 1.053Gbps 4×4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5μs, dual concurrent 173Mbps 2×2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n to 3GPP-LTE in 52μs. The main blocks from our versatile platform architecture are currently being prepared for tape-out.

High-level condition expression transformations for design exploration

Data intensive applications (i.e., multimedia) are clearly dominated by data transfer and storage issues. However, after removing the data transfer and address related bottlenecks, the control-flow mapping issues remain as important implementation overhead in a custom hardware realisation. The source of this overhead can be due to the presence of complex conditional code execution, loops or the mixed of both. In this work, we focus on optimising the behaviour of the conditional code which is dominated by complex condition test expressions. Our transformations aim in a first stage at increasing the degree of mutually exclusiveness of the initial condition trees. This step is complemented by optimising the decoding of the test expressions. In a second stage, architecture exploration is performed by trading-off at the high-level gate count against critical-path delay for the resulting code. We demonstrate the proposed transformations on a real-life driver using conventional behavioral synthesis tools as synthesis back-end. The driver selected represents the crucial timing bottleneck in a scalable architecture for MPEG-4 Wavelet Quantisation. Using our approach, we have explored in a very short time the design space at the high level and we have obtained a factor 2 reduction of the critical path with a smaller gate count overhead when compared to traditional RT or high-level synthesis based approaches, even when applied by experienced designers