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Dive into the research topics where Martin Pfost is active.

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Featured researches published by Martin Pfost.


IEEE Transactions on Electron Devices | 2017

Thermal Stability and Failure Mechanism of Schottky Gate AlGaN/GaN HEMTs

Manuela Mocanu; Christian Unger; Martin Pfost; P. Waltereit; Richard Reiner

This paper investigates the electrothermal stability and the predominant defect mechanism of a Schottky gate AlGaN/GaN HEMT. Calibrated 3-D electrothermal simulations are performed using a simple semiempirical dc model, which is verified against high-temperature measurements up to 440 °C. To determine the thermal limits of the safe operating area, measurements up to destruction are conducted at different operating points. The predominant failure mechanism is identified to be hot-spot formation and subsequent thermal runaway, induced by large drain-gate leakage currents that occur at high temperatures. The simulation results and the high temperature measurements confirm the observed failure patterns.


IEEE Transactions on Semiconductor Manufacturing | 2016

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

Matthias Ritter; Gimi Pham; Martin Pfost

In many automotive applications, repetitive self-heating is the most critical operation condition for LDMOS transistors in smart power ICs. This is attributed to thermo-mechanical stress in the on-chip metallization, which results from the different thermal expansion coefficients of the metal and the intermetal dielectric. After many cycles, the accumulated strain in the metallization can lead to short circuits, thus limiting the lifetime. Increasing the LDMOS size can help to lower peak temperatures and therefore to reduce the stress. The downside of this is a higher cost. Hence, it has been suggested to use resilient systems that monitor the LDMOS metallization and lower the stress once a certain level of degradation is reached. Then, lifetime requirements can be fulfilled without oversizing LDMOS transistors, even though a certain performance loss has to be accepted. For such systems, suitable sensors for metal degradation are required. This work proposes a floating metal line embedded in the LDMOS metallization. The suitability of this approach has been investigated experimentally by test structures and shown to be a promising candidate. The obtained results will be explained by means of numerical thermo-mechanical simulations.


international symposium on power semiconductor devices and ic's | 2017

Pulse robustness of AlGaN/GaN HEMTs with Schottky- and MIS-gates

Christian Unger; Manuela Mocanu; Martin Pfost; P. Waltereit; Richard Reiner

In this work we investigate the behavior of MIS- and Schottky-gate AlGaN/GaN HEMTs under high-power pulse-stress. A special setup capable of applying pulses of constant power is used to evaluate the electro-thermal response in different operating points. For both types of devices, the time to failure was found to decrease with increasing drain-source voltage. Overall, the Schottky-gate device displays a higher pulse robustness. The pulse withstand time of the MIS-gate device is limited by the occurrence of a thermal instability at approximately 240 °C while the Schottky-gate device displays a rapid increase of the gate leakage current prior to failure. The mechanism responsible for this gate current is further investigated by static and transient temperature measurements and yielded activation energies of 0.6 eV and 0.84 eV.


international semiconductor conference | 2016

Experimental analysis of the gate-leakage-induced failure mechanism in GaN HEMTs

Christian Unger; Manuela Mocanul; Martin Pfost; P. Waltereit; Richard Reiner

This work investigates the electro-thermal behavior and failure mechanism of a 600 V depletion-mode GaN HEMT by experimental analysis and numerical thermal simulations. For this device, the positive temperature coefficient of the drain-gate leakage current can lead to the formation of hot spots. This localized thermal runaway which ultimately results in a breakdown of the inherent drain-gate junction is found to be the dominant cause of failure.


international symposium on signals, circuits and systems | 2017

Optimal Power Point tracking for PV-systems with retrofitted Energy Storage Systems

Martin Wattenberg; Martin Pfost

This paper presents a control strategy for optimal utilization of photovoltaic (PV) generated power in conjunction with an Energy Storage System (ESS). The ESS is specifically designed to be retrofitted into existing PV systems in an end-user application. It can be attached in parallel to the PV system and connects to existing DC/AC inverters. In particular, the study covers the impact such a modification has on the output power of existing PV panels. A distinct degradation of PV output power was found due to the different power characteristics of PV panel and ESS. To overcome such degradation a novel feedback system is proposed. The feedback system continuously modifies the power characteristic of the ESS to match the PV panel and thus achieves optimal power utilization. Impact on PV and Maximum Power Point tracking performance is analyzed. Simulation of the proposed system is performed in MATLAB/Simulink. The results are found to be satisfactory.


international symposium on power semiconductor devices and ic's | 2017

Experimental study of the short-circuit performance for a 600V normally-off p-gate GaN HEMT

Thorsten Oeder; Alberto Castellazzi; Martin Pfost

In this paper, the short-circuit robustness of a normally-off GaN HEMT is investigated in relation to applied bias conditions and pulse duration. The results align with previous studies on normally-on devices in highlighting an electrical type of failure. Here, however, the relevance of the specific gate-drive circuit design and corresponding device operational conditions is demonstrated. A gate-bias dependence (GBD) of the failure, correlated to the applied drain-source voltage, is introduced as a novel specific feature for the p-Gate type device.


Microelectronics Reliability | 2017

Aging sensors for on-chip metallization of integrated LDMOS transistors under cyclic thermo-mechanical stress

Matthias Ritter; Martin Pfost

Abstract LDMOS transistors in integrated power technologies are often subject to thermo-mechanical stress, which degrades the on-chip metallization and eventually leads to a short. This paper investigates small sense lines embedded in the LDMOS metallization. It will be shown that their resistance depends strongly on the stress cycle number. Thus, they can be used as aging sensors and predict impending failures. Different test structures have been investigated to identify promising layout configurations. Such sensors are key components for resilient systems that adaptively reduce stress to allow aggressive LDMOS scaling without increasing the risk of failure.


Microelectronics Reliability | 2017

Electrical and thermal failure modes of 600 V p-gate GaN HEMTs

Thorsten Oeder; Alberto Castellazzi; Martin Pfost

A study of electrical and thermal failure modes of 600 V p-doped GaN HEMTs is presented, which focuses on the investigation of short-circuit limitations. The electrical failure mode seems to be an electrical field breakdown in the structure which is caused by excessive carrier concentration, rather than primary thermal generated. Accordingly, a thermal failure mode is observed, which features a distinctive behaviour and seems to be similar to schottky-gate HEMTs. Concerning the electrical failure mode, a specific p-gate HEMT short-circuit safe operating area (SCSOA) is presented as a novelty. However, a short-circuit capability of up to 520 V can be achieved, regarding the design of the gate-drive circuit.


international symposium on power semiconductor devices and ic s | 2018

40 V to 100 V NLDMOS built on thin BOX SOI with high energy capability, state of the art Rdson/BVdss and robust performance

Yang Hao; Sim Poh Ching; Madelyn Liew; Alexander Hoelke; Uwe Eckoldt; Martin Pfost


international symposium on power semiconductor devices and ic s | 2018

Influence of the off-state gate-source voltage on the transient drain current response of SiC MOSFETs

Christian Unger; Martin Pfost

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Christian Unger

Technical University of Dortmund

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Thorsten Oeder

Technical University of Dortmund

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Gimi Pham

Reutlingen University

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Asad Fayyaz

University of Nottingham

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