Martti Forsell

ON THE PERFORMANCE AND COST OF SOME PRAM MODELS ON CMP HARDWARE

The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures.

Realising constant time parallel algorithms with active memory modules

Recent advances in emulated shared memory architectures have made it possible to exploit the full power of a scalable parallel hardware in an easy-to-program form. Unfortunately, the obtained model of computing does not allow efficient parallel access to a single memory cell leaving the lower bound of the execution time of many important parallel algorithms logarithmic. In this paper, we describe a simple active memory based modification on memory module architecture that eliminates this limitation in many cases. Both algorithmic and real life examples are given. The resulting architecture can be used as a scalable processing infrastructure building block for general purpose applications like e-business, e-education, e-science, and e-medicine on the internet.

Reducing Power Consumption in Mobile Terminals—Video Computing Perspective

The high power consumption of video playback in mobile terminals has two major negative impacts. It limits the available operating time of the terminal devices deteriorating the user experience and contributes to the global energy consumption with negative environmental effects. Solutions to reduce the energy usage of mobile terminals include increasing the power efficiency of the terminal components, optimizing the video decoding and playback software as well as altering the quality and/or compression settings of the video data. While there exist some studies on power consumption with these means, most of them do not apply to state-of-the-art terminal hardware nor do they take a systematic approach to evaluate all available techniques. The focus of this chapter is on reducing the power consumption of mobile terminals as a part of video delivery system. For that, a wide variety of video computing-related energy-saving techniques is presented and evaluated on a line of Apple laptop mobile terminals running publicly available video playback software. The tests are done with video clips representing different kinds of video content and the effect of terminal hardware, video coding, video quality, player software, execution-environment/parameters and streaming to power consumption and data rate is measured. According to the measurements, the video computing induced consumption, total power consumption and data rate can be reduced with respect to the state-of-the-art situation in the beginning of the research by 83%, 65%, and 43%, respectively. Additional reductions can be achieved by decreasing the quality of videos, switching to smaller footprint devices, and replacing the current processors with more advanced ones.

HPPC 2010: 5th workshop on highly parallel processing on a chip

Despite the processor industry having more or less successfully invested already 10 years to develop better and increasingly parallel multicore architectures, both software community and educational institutions appear still to rely on the sequential computing paradigm as the primary mechanism for expressing the (very often originally inherently parallel) functionality, especially in the arena of general purpose computing. In that respect, parallel programming has remained a hobby of highly educated specialists and is still too often being considered as too difficult for the average programmer. Excuses are various: lack of education, lack of suitable easy-to-use tools, too architecture-dependent mechanisms, huge existing base of sequential legacy code, steep learning curves, and inefficient architectures. It is important for the scientific community to analyze the situation and understand whether the problem is with hardware architectures, software development tools and practices, or both. Although we would be tempted to answer this question (and actually try to do so elsewhere), there is strong need for wider academic discussion on these topics and presentation of research results in scientific workshops and conferences.