Maryline Bawedin

High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure

Two types of fin-shaped field-effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heterojunction-free GaN layer operating in junctionless mode, have been fabricated and characterized. The threshold voltages of both devices shift toward positive direction from large negative value as the fin width decreases. Both devices exhibit high ON-state performance. The heterojunction-free GaN FinFETs show superior OFF-state performance because the current flows through the volume of the GaN channel layer, which can be fully depleted. The proposed GaN nanochannel FinFETs are very promising candidates not only for high performance, but also for high power applications.

Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n Gated Diodes

Split capacitance measurements in thin SOI p-i-n gated diodes are performed and discussed. Contrarily to MOSFETs, the n+ and p+ contacts of the diode supply instantly minority and majority carriers preventing parasitic deep-depletion and transient effects. The gated diode enables accurate characterization from accumulation to strong inversion. We demonstrate that the diode capacitance curves provide extensive information, such as layer thickness and threshold voltage for both n- and p-type MOSFETs simultaneously. The experimental results are validated and explained through numerical simulations.

Floating-Body SOI Memory: The Scaling Tournament

In this paper, we present an overview of the typical device architectures of the single transistor capacitorless dynamic random access memory (1T-DRAM). This memory uses only one transistor and takes advantage of floating body effects in SOI and SOI-like devices. The principles of operation and key mechanisms for programming are described. The various approaches are compared in terms of architecture, performance and potential for aggressive scaling.

Mobility Investigation by Geometrical Magnetoresistance in Fully Depleted MOSFETs and FinFETs

The operation of advanced planar MOSFET and FinFET transistors on SOI is investigated under high magnetic field. The geometrical magnetoresistance is observed when the Hall field is suppressed thanks to the device geometry. This method is free from any assumptions (oxide and body thickness, effective channel length, etc.) and delivers the most accurate and indisputable value of carrier mobility. Our measurements show, for the first time, the mobility behavior in FinFETs with double- and triple-gate and in ultrathin SOI MOSFETs. The magnetoresistance reveals the electron mobility in front or back channels as well as the impact of their interaction. A marked difference in mobility value and variation with gate voltage between the front and back channels is highlighted. A mobility discrepancy also appears between planar and FinFET transistors. Nonuniversal mobility curves with multibranch aspect result from the coexistence of several channels. This nonconventional behavior is explained by the variations in effective field and inversion charge centroid. The geometric magnetoresistance effect arises even in the lateral channels of FinFETs, an intriguing aspect that results from the device configuration.

Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.

CMOS V T characterization by capacitance measurements in FDSOI PIN gated diodes

We present a powerful technique for the characterization of FDSOI devices. For example, in CMOS designs, the evaluation of threshold voltage for N and also P-MOSFETs is compulsory and is performed in separate devices. We propose to extract the threshold voltage for both types of transistors simultaneously by using capacitance measurements in thin fully depleted SOI PIN gated diodes. The N+ and P+ terminals guarantee the availability of both types of carrier and equilibrium conditions during all operation modes: from strong accumulation to strong inversion. Experiments together with numerical TCAD simulations are performed and discussed. It is shown that, from a single capacitance curve, it is possible to extract also the threshold voltage at the bottom interface.

Evidence of Sub-Band Modulated Transport in Planar Fully Depleted Silicon-on-Insulator MOSFETs

Modulation of the sub-band electron population in the inversion channel of 10-nm planar fully depleted silicon-on-insulator MOSFETs is evidenced by the bias dependence of inversion layer transport parameters. Two distinct inversion-layer electron species were detected by magnetic-field-dependent magnetoresistance measurements and high-resolution mobility spectrum analysis. According to self-consistent Poisson-Schrödinger calculations, these species correspond to carriers in distinct sub-bands within the Si channel region. The mobility peak of the carrier with the highest sheet density occurs under gate bias conditions that result in a minimum perpendicular effective electric field.

Magnetoresistance measurements and unusual mobilitiy behavior in FD MOSFETs

Advanced planar MOSFET and FinFET transistors on SOI have been characterized under high magnetic field. The geometrical magnetoresistance stands as the most accurate and indisputable technique for mobility measurements. Our results show that this method is also effective in both planar (FD-SOI) and vertical (FinFET) transistors with ultrathin body. For the first time, we apply the magnetoresistance for evaluating not only the properties of separate channels, but also their interaction mechanisms. Unconventional mobility curves with multi-branch aspect are recorded when two or more channels coexist. They are explained by the variations in effective field and centroid of the inversion charge. A marked difference is observed between front and back channels as well as between planar and FinFET devices.

Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs

In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back gate (ground plane). Based on devices simulations, we discuss the origin of the bipolar action, its suppression and the possible applications.

Why are SCE overestimated in FD-SOI MOSFETs?

Experimental results show that the measurement and interpretation of short-channel effects (SCE) are misleading in advanced SOI MOSFETs. Part of SCE is due to the parasitic contribution of the back gate via channel coupling. We demonstrate that the contributions of each gate to the overall SCE can be discriminated. Numerical simulations indicate that their mutual relevance depends on the transistor architecture. A pragmatic biasing method is proposed for the reduction of charge sharing and DIBL effects. We present a simple model which is effective in decorrelating the genuine SCE at each gate and can be advantageously applied to device optimization.