Masaaki Niwa

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

Physics in designing desirable ReRAM stack structure — Atomistic recipes based on oxygen chemical potential control and charge injection/removal

We clarify the importance of three-layers ReRAM stack-structures and provide guidelines for further optimization by both charge injection/removal and oxygen chemical potential. We determine atomistic structures corresponding to the ON-OFF switching process of ReRAMs using ab initio calculations. The cohesion-isolation of oxygen vacancies is found to be a strong driving force in the ON-OFF switching observed in oxide-based ReRAMs, and this phase transition can be controlled by injecting/removing charges while altering the oxygen chemical potential. Based on this concept, we propose universal guidelines for designing desirable ReRAM stack structures by introducing an oxygen vacancy barrier layer.

Fundamental origin of excellent low-noise property in 3D Si-MOSFETs ∼ Impact of charge-centroid in the channel due to quantum effect on 1/f noise ∼

We fabricated Si nanowire (NW) nFETs, and used them to experimentally demonstrate the superior noise properties of 3D MOSFETs. By carefully comparing the NWFETs with planar FETs, we found that it was critical to control the location of the centroid of the electron density in the inversion channel in order to obtain a noise spectral density with low magnitude. Self-consistent calculations of the Schrödinger and Poisson equations clearly reveal the advantages of NWFETs in electron distribution due to quantum confinement, specifically in the small gate-overdrive (Vg-Vt) condition. Moreover, by increasing Vd, the range where the NWFET exhibits superior noise properties to a planar FET can be extended to larger Vg-Vt because the effective Vg near the drain is reduced.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31 Si12 evaluated) for the 45 nm node. RTP1 and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer height control) opens the RTP1 process window from ~5degC to ~20degC for gate lengths down to 45nm, making scalable dual WF CMOS Ni-FUSI manufacturable. We demonstrate Vt control with sigma~19mV (including wafer to wafer variation, N=1000, 45 nm devices) for NMOS (NiSi), and sigma~21mV for PMOS. TDDB and NBTI reliability evaluation of NiSi and, for the first time, of Ni2Si and Ni31Si12 was done. ~1V or larger operating voltages (Vop) were extrapolated for a 10 years lifetime. Using a higher back-end thermal budget showed no reliability degradation

Physical Guiding Principles for High Quality Resistive Random Access Memory Stack with Al2O3 Insertion Layer

We theoretically clarified the atomistic role of the Al2O3 oxygen vacancy (VO) barrier layer in advanced ReRAM stacks. We found that VO filament formation in Al2O3 can be controlled by applying voltage when the Al2O3 layer is in contact with VO source layer such as Hf, although VO formation in Al2O3 is difficult in usual situation. Moreover, we proposed a physical guiding principle toward designing high quality ReRAM stacks with Al2O3 VO barrier layers.

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

We report for the first time on the use of a Ni fully germano-silicide (FUGESI) as a metal gate in pFETs. Using HfSiON dielectrics and comparing to Ni FUSI devices, we demonstrate that the addition of Ge in poly-Si gate results in 1) Fermi-level unpinning with >200 mV increase in work function; 2) improved dielectrics integrity: such as decreased 1/f and generation-recombination noise, improved channel interface, reduced gate leakage, and superior NBTI characteristics. The above experimental observations are correlated to oxygen vacancies related defects in the HfSiON layer

Stress polarity dependence of the activation energy in time-dependent dielectric breakdown of thin gate oxides

Stress polarity dependence of the activation energies in the two time dependent dielectric breakdown measurements, the constant-current injection (Q/sub bd/ testing) and the constant-voltage stressing (t/sub bd/ testing) are investigated for gate oxides with the thickness ranging from 10 to 4 nm. A remarkable polarity dependence of the activation energies appears in the t/sub bd/ testing when the oxide thickness decreases. This phenomenon is found to be due to a characteristic temperature dependence of the gate current density during the whole t/sub bd/ testing period for thinner oxides, which is considered as a result from the temperature dependence of the electron trapping process during the stressing.

Correlation between lifetime, temperature, and electrical stress for gate oxide lifetime testing

A relationship between the gate oxide lifetime (t/sub bd/), temperature (T), and the electrical stress for the reliability testing is investigated. Based on the various lifetime testing results reported by previous investigators, a new parameter for the oxide lifetime prediction is introduced. The parameter T[log(t/sub bd/)+C], where C is a constant, has a linear relationship with respect to the electrical stress field in the oxide. By using the above parameter, it becomes easy to describe and compare the characteristics of oxide reliability on one graph.

Current fluctuation in sub-nano second regime in gate-all-around nanowire channels studied with ensemble Monte Carlo/molecular dynamics simulation

The impact of current fluctuation due to discreteness in carrier numbers on high-frequency noise amplitudes is numerically investigated, focusing on the comparison to the impact of a single trapped charge in the oxide layer for gate-all-around nanowire structures. The variation in the amount of the charge transporting through the channel within a single clock cycle is estimated. The transported charge variation due to the current fluctuation clearly shows the universality with respect to the total amount of the transported charge. It concludes that the current fluctuation becomes a dominant noise source over 100 GHz range.

First principles guiding principles for the switching process in oxide ReRAM

First principles calculations became crucial techniques for designing future electronics engineering. In this paper, we describe the typical examples which aim the designing of future electron devices such as modern resistive random access memories (ReRAM) by using the knowledge obtained by the first principles calculations.