Masaharu Goto
Agilent Technologies
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Publication
Featured researches published by Masaharu Goto.
IEEE Transactions on Very Large Scale Integration Systems | 2014
Tseng-Chin Luo; Mango Chia-Tso Chao; Huan-Chi Tseng; Masaharu Goto; Philip A. Fisher; Yuan-Yao Chang; Chi-Min Chang; Takayuki Takao; Katsuhito Iwasaki; Cheng Mao Lee
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layout-dependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (Vt) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, Vt must be measured for a sufficiently large number of device-under-tests (DUTs) to obtain a statistically representative sample population. The number of Vt measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve Vt testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ~2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of Vt = 0.15 mV, versus typical accuracy of ~ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.
international conference on microelectronic test structures | 2010
Yasuhiro Miyake; Masaharu Goto; Shunsuke Fujii; Hidetoshi Nishimura
This paper reports capacitance measurement correlation between Direct Charge Measurement (DCM) and conventional LCR meter on 0.18um CMOS test structure. Measurement results of interconnect and MOSCAP test structures are presented. Mathematical analysis shows that DCM and LCR meter results correlate very well for MOSCAP as well. Amplitude Adjustment Method and Amplitude Extrapolation Methods are proposed to calibrate nonlinear C-V measurement errors. Theoretical discussion can also be applied to Charge-Based Capacitance Measurement (CBCM) because it uses similar stimulus.
international conference on microelectronic test structures | 2009
Yasuhiro Miyake; Masaharu Goto
This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip active device. Measurement results of silicon and glass substrates, including parallel measurements, are presented.
IEEE Transactions on Semiconductor Manufacturing | 2013
Masaharu Goto; Yasuhiro Miyake; Jun Taniguchi; Kenichi Takano
A fast and accurate capacitance measurement technique, direct charge measurement (DCM), is introduced to improve productivity of semiconductor parametric testing. The approach is simpler and much faster compared with conventional method using charge-based capacitance measurement (CBCM) or LCR meter. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. The basic theory, parallel measurement method and mathematical analysis on non-linear MOS capacitance measurement are explained. For interconnect capacitance measurement, an extension of DCM, degenerated exhaustive direct charge measurement (DEDCM) is presented as a faster, more accurate and thorough characterization technique. Experimental results show good data matching and significant throughput improvement over conventional LCR meter measurements.
international conference on microelectronic test structures | 2016
Kenichi Takano; Masaharu Goto; Emesto Shiling; Arthur Gasasira; Jiun-Hsin Liao
Direct Charge Measurement (DCM) has a capability to improve the capacitance measurement time in parametric test. Through an actual wafer measurement, we have successfully verified that DCM can measure MOS capacitor much faster than an LCR meter while keeping good correlations for wafer manufacturing.
international conference on microelectronic test structures | 2012
Masaharu Goto; Jun Taniguchi; Kenichi Takano
Continuing scaling down trend of semiconductor process node has increased the necessity of comprehensive interconnect capacitance testing, however, the measurement has only been made between limited combinations of conductor groups due to test time constrains. In this paper, we propose new interconnect capacitance measurement method, Degenerated Exhaustive Direct Charge Measurements (DEDCM). This method enables measuring all interconnect capacitance components accurately and faster.
Archive | 2006
Masaharu Goto
Archive | 2004
Tomoya Fujisaki; Masaharu Goto
Archive | 2009
Masaharu Goto; Minoru Uchida; Koji Tokuno
Archive | 2014
Katsuhito Iwasaki; Masaharu Goto; Tomonori Ura