Masahide Hatanaka

Owens Luis — A context-aware multi-modal smart office chair in an ambient environment

This paper introduces a smart office chair, Owens Luis, whose pronunciation has a meaning of “an encouraging chair (****)” in Japanese. For most of the people, office environments are the place where they spend the longest time while awake. To improve the quality of life (QoL) in the office, Owens Luis monitors an office workers mental and physiological states such as sleepiness and concentration, and controls the working environment by multi-modal displays including a motion chair, a variable color-temperature LED light and a hypersonic directional speaker.

Implementation of OFDM baseband transceiver with dynamic spectrum access for cognitive radio systems

VLSI architecture for OFDM baseband transceiver is developed, which is dedicated to cognitive radio systems. To facilitate dynamic spectrum access, this transceiver architecture employs a specialized FFT/IFFT module and a mapping/demapping module. Efficient mechanisms to omit input/ output of unused subcarriers are introduced. Also, calculation of spectrum intensity for subcarrier level carrier sensing is successfully integrated to the FFT module. Whole transmitter/ receiver modules are implemented by keeping compatibility with IEEE 802.11g. A prototype system is constructed by using Xilinx Virtex-II FPGA, which can transmit video sequence in real time.

VLSI design of OFDM baseband transceiver with dynamic spectrum access

The VLSI design of OFDM baseband transceiver is described, which is dedicated to cognitive radio systems. To facilitate dynamic spectrum accessing, this receiver architecture employs a specialized FFT module and a mapping/demapping module. Efficient mechanisms to omit input/output of unused subrcarriers are introduced. Also, calculation of spectrum intensity for subcarrier level carrier sensing is successfully integrated to the FFT module. Whole transmitter/receiver modules are implemented by maintaining compatibility with IEEE 802.11g. Implementation results show that the proposed architecture can process OFDM symbols in 60 MHz operation.

Design of generic hardware for soft cascade-based linear SVM classification

Support Vector Machine is renowned as a powerful machine learning algorithm for many classification problems. However, among all the works proposed for SVM hardware implementation, a lot of them are designed with predefined settings for specific objective, rendering them usable only for single or few purposes. This paper presents an SVM hardware architecture capable of classifying input data with arbitrary vector dimensionality and arbitrary precision, resulting in a generic support vector machine capable of classifying various targets. The proposed architecture also employs a speed-up method called soft cascade algorithm to enhance its performance. To assess its hardware implementation, it is synthesized in two styles using Xilinx FPGA and NanGate Open Cell Library. The results show a feasible circuit scale implementation, and when used for CoHOG pedestrian detection, the proposed hardware architecture is estimated to be capable of classifying up to 79 VGA images per second on FPGA and up to 35 HD images per second on 45nm process technology circuit, even under the condition that the architecture is not designed specifically for the aforementioned purpose.

Architecture and implementation of fading compensation for dynamic spectrum access wireless communication systems

This paper proposes an efficient architecture and implementation of fading compensation dedicated to dynamic spectrum access (DSA) wireless communication. Since pilot subcarrier arrangements are adaptively determined in wireless communication systems with DSA, the proposed architecture employs piecewise linear interpolation to the channel response estimation for data subcarriers in order to increase the channel estimation accuracy. The fading compensation for an orthogonal frequency-division multiplexing (OFDM) symbol isperformedwithinthe time foroneOFDMsymbol tomake increase of latency smaller. Theproposedarchitecture guarantees real-time processing with 76MHz or higher clock frequency. The FPGA implementation of the proposed architecture occupies 1,577 slices and works up to 121MHz.