Masahiro Hosoya

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.

A 900-MHz bandwidth analog baseband circuit with 1-dB step and 30-dB gain dynamic range

A wide-bandwidth analog baseband circuit with digital gain control is implemented in a 65-nm CMOS process. The proposed circuit adopts a variable transconductance amplifier, which achieves constant bandwidth regardless of the gain settings. Bandwidth variation is less than ±1.2 % within the gain control range of 20 dB. The proposed analog baseband circuit has in-phase and quadrature-phase paths and draws 24.8 mA from a 1.2-V power supply. Measured results show that 1-dB step gain control with 0.25-dB differential nonlinearity (DNL) for 30-dB range and I/Q gain matching accuracy of 0.15 dB is achieved.

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

Investigation of the organic solar cell characteristics for indoor LED light applications

We report an experimental study on the current–voltage characteristics of organic solar cells (OSCs) under indoor light illumination. A daylight color light-emitting diode (LED) was used as the indoor light source. We investigated the short circuit current density, open circuit voltage, and fill factor of the OSC under LED irradiation and compared them with those for a crystal silicon solar cell (c-Si-SC), which occupy a large part of the solar cell market. We found that compared with the c-Si-SC, the OSC had higher power conversion efficiency (PCE). We also derived the maximum feasible PCE of an OSC for indoor applications and calculated that a PCE value of 21.3% could be obtained under daylight color LED illumination at approximately 200 lx. From the results of the calculation, it became apparent that the open circuit voltage plays an important role in achieving a high PCE from OSCs, indicating they are promising as electrical energy harvesting module for indoor applications.

A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization

Recently, signals with high peak-to-average power ratio (PAPR) are being used for metropolitan area networks (MANs) and cellular systems, and therefore highly linear transmitters (Txs) are required. The linearity performance can be improved by operating a power amplifier (PA) with large back-off; however, it sacrifices the efficiency. Therefore, a Tx linearizer is required to satisfy the error-vector magnitude (EVM) and adjacent-channel-leakage ratio (ACLR) requirements with smaller back-off. Since highly efficient PAs fabricated in GaAs or SiGe processes are preferred for these applications, a linearizer for an off-chip PA is desired.

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (analog base-band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (high speed downlink packet access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (digital base-band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (high speed packet access) and GSM/EDGE.

0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop

A 0.13 mum CMOS Cartesian loop transmitter IC with calibration and loop setting scheme of less than 5 mus is fabricated in order to keep high efficiency in wide output power range. The proposed scheme adjusts amplitude, phase, loop gain by using TX modulated signal for fast loop setting. Adjacent channel power leakage ratio (ACPR) is improved by 18 dB. The transmitter IC without PA consumes 62 mA, in which feedback path consumes 22 mA.

Xerographic development using single-component nonmagnetic toner

No magnetic material is necessary for this system. A thin layer of nonmagnetic toner is formed on the surface of a metal roller by means of an elastic plate which is pressed against the roller. The toner particles are charged triboelectrically by friction with the metal plate. The toner layer is attached to the roller by electrostatic force, and is carried around to the photosensitive drum. The latent image is developed with the noncontact development technique. The insulative toner developed for this system has a superior triboelectric characteristic. A model for toner charging is shown. The numerical calculations based on the model agree well with the experimental results. The model suggests that the metal plate controls the toner charge. >

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier

This paper presents a 3-GS/s 5-bit interpolated Flash ADC with a wideband input buffer amplifier. Small input capacitance of the ADC is necessary to achieve high signal bandwidth with low power consumption of the input buffer. The design challenge is a reduction of power consumption of the interpolated Flash ADC and the input buffer simultaneously. To solve this, the interpolation technique using reference voltages is proposed to reduce the input capacitance and interpolated stages simultaneously. The prototype is fabricated in a 65-nm CMOS technology. The measured results show that the cutoff frequency is 1.6 GHz, the peak spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) are 33.1 dB and 23.1 dB at nyquist frequency, respectively. The power consumption including the input buffer is 39.4 mW, and the Figure of Merit (FoM) of 0.58 pJ/conversion-step is achieved.

Carrier generation in fullerenes

The efficiency of carrier generation by the zerographic discharge technique has been measured on four films; a molecularly C60-doped polymer film, a molecularly C70-doped polymer film, an aggregate C60 film, and an aggregate C70 film. The yield for molecularly C70-doped polymer was three orders of magnitude larger than that for the film of molecularly C60-doped polymer. The photon energy dependence of efficiency for the aggregate films differed from that for the molecularly doped polymer films. The carrier generation efficiency spectrum for the aggregate films showed peaks corresponding to the Frenkel type excitons. The sensitivity of a photoreceptor fabricated with C70 was 0.5(cm2/(mu) J) at wavelengths in the 420nm-670nm region.