Masahiro Kanazawa

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design.

Automated low-power technique exploiting multiple supply voltages applied to a media processor

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance,.

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.

Low-power design technique for ASICs by partially reducing supply voltage

In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing one to reduce power without performance degradation. As a result of application to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing became less effective. The CVS is considered to be a key technique toward the deep sub-micron age, in which the wire capacitance will be further dominant.