Masahiro Moniwa

Low-temperature SOI (Si-on-insulator) formation by lateral solid-phase epitaxy

Low‐temperature (550–600 °C) formation of a Si‐on‐insulator structure by a solid‐phase process is investigated. A microprobe (μ) reflection high‐energy electron diffraction observation reveals that oriented crystal growth propagates from the seeding area in solid‐phase epitaxy (SPE). The effects of random nucleation, epitaxial alignment, and local doping on lateral (L)‐SPE are examined. As a result, a relatively large L‐SPE area, 14 μm from the seeding area, is achieved on insulating regions. Crystal quality and electrical properties of L‐SPE layers are examined using μ‐Raman spectroscopy and field‐effect transistor fabrication. A small stress field, 2.5×109 dyn/cm2, and high electron mobility, 720 cm2/V s, comparable to that of bulk Si are obtained.

Preferential nucleation along SiO2 steps in amorphous Si

Annealing characteristics for amorphous Si film deposited on an SiO2 layer were investigated with the hope that this would throw further light on aspects of solid phase epitaxy. Preferential nucleation, which initiated from the bottom region of deposited Si film, was found along SiO2 steps. The activation energy for the growth speed of the nuclei was evaluated to be 1.7 eV. As this value is significantly smaller than 2.0 eV, the bond breaking energy of Si, stress originating mainly from the thermal expansion difference between SiO2 and Si, is considered to be the driving force.

Focused ion beam gallium implantation into silicon

The electrical properties and lattice disorders of 50 keV, focused ion beam (FIB) gallium-implanted silicon layers have been investigated as a function of beam scan speed and ion dose. The critical dose for continuous amorphous layer formation is 8 ∼ 10 × 1013 ions/cm2, when the beam scan speed is lowered to about 10−2 cm/s. This is about 1/3 that of conventional ion implantation. The increase in secondary defect formation after annealing is also observed as the beam scan speed decreases under implantation conditions close to the critical dose. However, the effect of high dose rate on the electrical activation of gallium atoms and critical dose reduction is not as significant as with FIB implantation by a lighter ion mass, such as boron. The results are compared with those obtained by conventional ion implantation.

I-V measurement of NiO nanoregion during observation by transmission electron microscopy

Conduction measurements with simultaneous observations by transmission electron microscopy (TEM) were performed on a thin NiO film, which is a candidate material for resistance random access memories (ReRAMs). To conduct nanoscale experiments, a piezo-controlled TEM holder was used, where a fixed NiO sample and a movable Pt-Ir counter electrode were placed. After the counter electrode was moved to make contact with NiO, I-V measurements were carried out from any selected nanoregions. By applying a voltage of 2 V, the insulating NiO film was converted to a low resistance film. This phenomenon may be the “forming process” required to initialize ReRAMs. The corresponding TEM image indicated a structural change in the NiO layer generating a conductive bridge with a width of 30–40 nm. This finding supports the “breakdown” type forming in the so-called “filament model” of operation by ReRAMs. The inhomogeneity of resistance in the NiO film was also investigated.

Process and properties of Pt/Pb(Zr, Ti)O3/Pt integrated ferroelectric capacitors

Abstract A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

Controlling the Solid-Phase Nucleation of Amorphous Si by Means of a Substrate Step Structure and Local Phosphorus Doping

We propose a solid-phase crystallization technique that controls the location of crystal grain formation on SiO2 substrates. This enables the formation of electronic devices in a single grain. To determine the condition of the technique, the nucleation characteristics of amorphous Si with P- and B-doping are investigated. Also, the characteristics with and without step structures on the substrate surface are reported and discussed. The various nucleation behaviors can be interpreted in terms of the critical size of the nucleus and of the rate of crystal growth.

A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.

Influence of Si film thickness on growth enhancement in Si lateral solid phase epitaxy

Lateral solid phase epitaxial growth (L‐SPE) of Si on SiO2 film was investigated as a function of deposited amorphous Si (a‐Si) film thickness. Both the L‐SPE rate and the annealing time necessary for {111} facet formation increased with film thickness. As a result, a large L‐SPE length (9 μm) under {110} facet growth was obtained for a 1.6‐μm‐thick film sample. Above the critical film thickness (>2 μm), crack formation in a‐Si films was observed during deposition. This indicates that intrinsic stresses play an important role in this growth enhancement.

A new method for predicting distribution of DRAM retention time

A new method for predicting the distribution of retention time of a dynamic random access memory (DRAM) by using the test element group (TEG) has been developed. The TEG is constructed of memory cells which are connected in parallel, so that the sum of memory-cell leakage currents can be measured. We verified that the t/sub ret/ main distribution can be statistically predicted from the distribution of TEG leakage current. Furthermore, we determined the measurement condition for detecting some TEGs that contain anomalously leaky cells, which limit the DRAM refreshing interval.

Floating Gate Memory with Biomineralized Nanodots Embedded in High-k Gate Dielectric

The memory properties of a nanodot-type floating gate memory with Co bio-nanodots (Co-BNDs) embedded in HfO2 were investigated. High-density and uniform Co-BNDs were adsorbed on the HfO2 tunnel oxide using ferritin. The fabricated metal oxide semiconductor (MOS) capacitor exhibited a capacitance–voltage (C–V) curve with large hysteresis. The memory window size was 30 times higher than that of the MOS capacitor with a SiO2 gate oxide. Not only a large memory window but also excellent charge retention and reliability characteristics were obtained for a MOS field-effect transistor (MOSFET). This research confirmed that the proposed memory is promising for use in next-generation memory devices.