Masamichi Okamura

Slow Current-Drift Mechanism in n-Channel Inversion Type InP-MISFET

The current drift mechanism inherent in n-channel inversion type InP-MISFETs were investigated. From comparison of drift behavior of InP-MISFET with that of Si-MISFET (fabricated in the same manner as that of InP-MISFET) and measurement of its temperature dependence, it was found that the drift originated from electron trappings, and the trapping centers located in the CVD-Al2O3 gate insulator and in the InP native oxide surface layer. Because of higher concentration of trapping centers (one order of magnitude higher than that of Al2O3 insulator), the InP native oxide served as the main cause of the observed current drift. The trap level and concentration in the native oxide were estimated to be ?38 meV above Fermi level and 1.5?1017/cm3, respectively.

Improved Interface in Inversion-Type InP-MISFET by Vapor Etching Technique

A new fabrication technique for the inversion-type InP-MISFET is proposed in order to improve the serious current drift. The native oxide layer grown on the InP crystal surface was removed by the HCl vapor etching technique (1000 A in depth) prior to deposition of the gate insulator (CVD-Al2O3). By this technique, the electron trapping centers inside the InP native oxide, the main cause of the drain current drift, were almost completely removed, and improved drain current characteristics could be achieved.

Effect of pyrolytic Al2O3 deposition temperature on inversion‐mode InP metal‐insulator‐semiconductor field–effect transistor

The effects of pyrolytic Al2O3 deposition temperature on electrical properties of an inversion‐mode InP (MISFET) metal‐insulator‐semiconductor field‐effect transistor were investigated. An Al2O3 gate insulator was deposited using an aluminum isopropoxide organic source on a HCl vapor etched InP surface. An increasing current drift was seen when the insulator was deposited at a temperature below 330 °C. This became exaggerated with decreasing temperature. The observed drift is explained in terms of a time‐dependent threshold voltage associated with the polarization of organic molecules or radicals introduced into the insulator by an incomplete decomposition of the source gas during deposition of the dielectric layers at rather low temperatures. The effective electron mobility of the InP MISFET did not show any dependence on the deposition temperature below 350 °C. At higher temperatures, the effective mobility appreciably decreased.

Infrared photodetection using a-Si:H photodiode

It is experimentally demonstrated for the first time that an a-Si:H photodiode with reach-through structure can detect infrared light of 1.31 /spl mu/m and 1.55 /spl mu/m. A maximum gain-quantum efficiency product of 0.58 is obtained at a reverse bias of /spl minus/10 V under 100 /spl mu/W illumination at 1.31 /spl mu/m. This value of gain-quantum efficiency product is comparable to the quantum efficiency of a non-gain-enhanced a-Si:H pin photodiode at visible wavelengths.<<ETX>>

Hysteresis free SiO2/InSb metal‐insulator‐semiconductor diodes

Hysteresis free capacitance‐voltage (C‐V) characteristics of SiO2/InSb metal‐insulator‐semiconductor (MIS) diodes are attained by introducing an in situ Br vapor etching technique into the fabrication process. Interface state density is also reduced by using this technique. It is found that following vapor etching, MIS C‐V characteristics are strongly dependent on both the SiO2 film deposition temperature and oxygen flow rate. The optimum condition for SiO2 film deposition to obtain hysteresis free C‐V curves and an interface state density of ≤1×1011 cm−2 eV−1 is determined for InSb MIS diodes. The area of the typical optimum conditions for MIS diodes is located in the oxygen flow rate range of 5–6 cc/min and the deposition temperature range of 200–210 °C. The refractive indices of SiO2 films are 1.44–1.45, the breakdown field strengths are more than 2×106 V/cm, and the dielectric constants for 1 MHz are typically 4.7 at 77 K, respectively.

The effects of annealing metal‐insulator‐semiconductor diodes employing a thermal nitride‐InP interface

The interface properties of the thermal nitride film‐InP system and its annealing were investigated. To obtain a uniform thermal nitride on a InP crystal, an improved thermal nitriding technique was developed by introducing in situ HCl vapor etching prior to the thermal nitriding. Two devices [MANS (metal‐alumina‐nitride‐semiconductor) diode and FET (field‐effect‐transistor)] containing a composite gate insulator of a thin nitride film (∼100 A) and CVD (chemical‐vapor‐deposition)‐Al2O3 film (∼1000 A) were compared with conventional MAS devices in view of the surface state density (NSS) in the MANS interface at energies near the conduction band edge decreased from 1×1013 to 1×1012/cm2 eV after annealing at 550 °C. A considerable increase in the effective mobility of the MANS‐FET was also seen after annealing. However, further annealing at a temperature higher than 600 °C resulted in a gradual degradation in the interface quality. In contrast, only the MAS interface showed degradation. Discussions are given...

Film deposition temperature dependence of electron mobility for accumulation‐mode InP metal‐insulator‐semiconductor field‐effect transistors

The effects of substrate temperature during film deposition on semi‐insulating InP metal‐insulator‐semiconductor field‐effect transistor characteristics are reported. The substrate temperature during film deposition, Ts, has a large influence on elastic and inelastic electron scattering times. With decreasing Ts, effective mobilities measured at room temperature and at 77 K increase, and the temperature dependence of effective mobility is more clearly observed. Electron scattering by neutral impurities is calculated in order to estimate the number of scattering centers near the InP surface, and to determine the activation energy (Ea=0.3±0.1 eV) of phosphorus migration (i.e., P hopping). Hikami–Larkin–Nagaoka’s theory [Prog. Theor. Phys. 63, 707 (1980)] is applied to negative‐magnetoresistance data measured at low temperature and in the low induced electron density region to estimate the electron inelastic scattering times. The substrate temperature dependence of inelastic scattering time is discussed in t...

An integrated photodetector-amplifier using a-Si p-i-n photodiodes and poly-Si thin-film transistors

The authors propose a photodetector-amplifier circuit consisting of a bridge photodetector circuit and a CMOS differential amplifier, both monolithically integrated on a transparent substrate. A test circuit was fabricated using a-Si p-i-n photodiodes and poly-Si thin-film transistors on a quartz substrate. A clear effect of the differential amplifier was demonstrated in the test circuit. It is shown that the circuit performance can be controlled by changing the bias current of the differential amplifier. With a relatively low bias current on the order of 10/sup -11/ A, the circuit works digitally with output voltages either close to 0 V or V/sub DD/. The power consumption of the circuit is approximately 60 mu W, which is low enough for use in two-dimensional arrays.<<ETX>>

Surface controlled InP‐MIS (metal‐insulator‐semiconductor) triodes

Surface controlled InP‐MIS (metal‐insulator‐semiconductor) triodes were fabricated and applied as efficient surface luminescence devices and as a more direct measurement of the surface inversion charge density. Sufficient surface luminescence was obtained under an applied pulse gate bias as low as a few volts. The radiation intensity was in proportion to the pulse repetition frequency (0.2–4 MHz). From measurement of the surface controlled MIS current, the surface inversion charge density was estimated more directly. The inversion charge density was closely correlated with the surface‐state density Nss, which was deduced to be ∼1013/cm2 eV from comparison of the experimental results with a simple analysis.

The Effect of Fe Concentration in Substrates on the Characteristics of InP MISFETs

The relationship between the characteristics of accumulation-type InP MISFETs and the Fe concentrations in their semi-insulating sustrates has been investigated. It was learned that the effective electron mobilities decrease with an increase in the Fe concentration. It was also observed that the threshold voltages shift in the positive direction with an increase in the Fe concentration.