Masanori Muroyama

Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

An SOI tactile sensor with a quad seesaw electrode for 3-axis complete differential detection

This paper presents a novel SOI capacitive tactile sensor with a quad-seesaw electrode for 3-axis complete differential detection, which enables integration with a CMOS. For differentially detecting 3-axis forces, the tactile sensor is composed of four rotating plates individually suspended by torsion beams. In this study, to demonstrate the working principle, we fabricated a test device that integrates an SOI substrate with the quad-seesaw electrode and an anodically bondable LTCC substrate with fixed electrodes as an alternative to the CMOS. The experimental results of the test device successfully demonstrated the working principle as well as 3-axis differential detection with a matrix operation.

Development of ballistic hot electron emitter and its applications to parallel processing: active-matrix massive direct-write lithography in vacuum and thin-film deposition in solutions

Abstract. Making the best use of the characteristic features in nanocrystalline Si (nc-Si) ballistic hot electron source, an alternative lithographic technology is presented based on two approaches: physical excitation in vacuum and chemical reduction in solutions. The nc-Si cold cathode is composed of a thin metal film, an nc-Si layer, an n+-Si substrate, and an ohmic back contact. Under a biased condition, energetic electrons are uniformly and directionally emitted through the thin surface electrodes. In vacuum, this emitter is available for active-matrix drive massive parallel lithography. Arrayed 100×100 emitters (each emitting area: 10×10  μm2) are fabricated on a silicon substrate by a conventional planar process, and then every emitter is bonded with the integrated driver using through-silicon-via interconnect technology. Another application is the use of this emitter as an active electrode supplying highly reducing electrons into solutions. A very small amount of metal-salt solutions is dripped onto the nc-Si emitter surface, and the emitter is driven without using any counter electrodes. After the emitter operation, thin metal and elemental semiconductors (Si and Ge) films are uniformly deposited on the emitting surface. Spectroscopic surface and compositional analyses indicate that there are no significant contaminations in deposited thin films.

Delay window blind oversampling clock and data recovery algorithm with wide tracking range

A new blind oversampling clock and data recovery (BO-CDR) algorithm is proposed. It has high tolerance to low-frequency jitter (14.8 unit intervals at 10 kHz, measured at 640 Mbps) and is suitable for systems where the receiver clock has high drift with respect to the transmission. The algorithm is capable of recovering data over a wide tracking range or when the precise oversampling rate (β) is not known a priori, for any real-valued oversampling rate, β ≥ 3, making this BO-CDR algorithm the first to not require integer-valued β. To demonstrate the utility of the algorithm, two implementations are designed and evaluated. The first is used in a low-power, low-data rate sensor node IC with a low-performance single phase clock source. The second is a high-speed receiver with a multiple phase clock source implemented on FPGA. The CDR core consists of just 47 logic cells and 19 registers and has an estimated power consumption of 0.70 mW at 640 Mbps. The properties of this CDR algorithm make it appropriate for a wide range of applications in serial communication.

Integration and packaging technology of MEMS-on-CMOS tactile sensor for robot application using molded thick BCB layer and backside-grooved electrical connection

This paper describes a novel integration and packaging process for a chip-size-packaged integrated tactile sensor. A MEMS wafer and a CMOS wafer were bonded with a thick (50 µm thick) BCB (benzocyclobutene) layer, which also works as the dielectric layer of sensing electrodes. The large thickness is advantageous to reduce parasitic capacitance to the CMOS circuit. The thick BCB layer was formed on the CMOS wafer and molded with a glass mold to make a flat surface with via holes. For surface mounting, bond pads are located on the backside of the senor chip by drawing electrical feed lines through the chip edge. To make the feed lines in wafer level, tapered grooves were fabricated along the scribe lines by TMAH wet etching, and half dicing was done along the grooves to access electrodes on the BEOL layer. Finally, the tactile senor was completed and preliminarily evaluated.

Fully-integrated, fully-differential 3-axis tactile sensor on platform LSI with TSV-based surface-mountable structure

The present paper reports a 2.8-mm-square surface-mountable MEMS-on-LSI integrated 3-axis tactile sensor for robot applications, which incorporates sensing and signal processing in a single chip. The MEMS part has a quad-seesaw-electrode structure for fully-differential capacitive 3-axis force sensing. The LSI is an original sensor platform LSI equipped with deep annular-type through silicon vias (TSVs). A multi-project LSI wafer was processed after fabrication in an LSI foundry. The MEMS part and the LSI part were integrated by Au-Au thermocompression bonding. The output is a digital packet and is transferred through the TSV and a bus line. A working test successfully demonstrated the fully-differential capacitive 3-axis force sensing of the fully-integrated tactile sensor.

A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications

Robot tactile sensation can enhance human–robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as “sensor platform LSI”) as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated.

3-Axis fully-integrated surface-mountable differential capacitive tactile sensor by CMOS flip-bonding

This paper reports a 3-axis MEMS-CMOS integrated tactile sensor for surface-mounting on a flexible bus line. This 3-axis sensor uses a bran-new CMOS LSI with capacitive sensing circuit and other extended functionalities (e.g. configurability and a robust clock data recovery algorithm). The sensor is composed of a flip-bonded CMOS substrate with a sensing diaphragm and a special low temperature co-fired ceramics (LTCC) substrate with vias. These substrates are electrically and mechanically connected by Au-Au bonding, forming sealed differential capacitive gaps. The completed sensor outputs coded 3-axis digital signals according to applied 3-axis force with small cross-sensitivity and hysteresis.

Flipped CMOS-diaphragm capacitive tactile sensor surface mountable on flexible and stretchable bus line

The following novel configuration has been developed for a MEMS-CMOS integrated tactile sensor on a flexible and stretchable bus for covering a social robot body: a sensing diaphragm is formed on a CMOS substrate by backside etching, and the CMOS substrate is flip-bonded to a low temperature co-fired ceramic (LTCC) substrate. By this configuration, no through-silicon vias (TSVs) are needed, simplifying the fabrication process. The flipped CMOS substrate and the LTCC substrate were bonded and electrically connected using Au-Au bonding, which also formed differential capacitive gaps. A flexible and stretchable wire was fabricated by metal etching and polyimide laser cutting. The tactile sensors, which were mounted on the surface of the flexible bus, sent coded digital signals according to applied force.

Development of maskless electron-beam lithography using nc-Si electron-emitter array

This study demonstrated our prototyped Micro Electro Mechanical System (MEMS) electron emitter which is a nc-Si (nanocrystalline silicon) ballistic electron emitter array integrated with an active-matrix driving LSI for high-speed Massively Parallel Electron Beam Direct Writing (MPEBDW) system. The MPEBDW system consists of the multi-column, and each column provides multi-beam. Each column consists of emitter array, a MEMS condenser lens array, an MEMS anode array, a stigmator, three-stage deflectors to align and to scan the multi beams, and a reduction lens as an objective lens. The emitter array generates 100x100 electron beams with binary patterns. The pattern exposed on a target is stored in one of the duplicate memories in the active matrix LSI. After the emission, each electron beam is condensed into narrow beam in parallel to the axis of electron optics of the system with the condenser lens array. The electrons of the beams are accelerated and pass through the anode array. The stigmator and deflectors make fine adjustments to the position of the beams. The reduction lens in the final stage focuses all parallel beams on the surface of the target wafer. The lens reduces the electron image to 1%-10% in size. Electron source in this system is nc-Si ballistic surface electron emitter. The characteristics of the emitter of 1:1 projection of e-beam have been demonstrated in our previous work. We developed a Crestec Surface Electron emission Lithography (CSEL) for mass production of semiconductor devices. CSEL system is 1:1 electron projection lithography using surface electron emitter. In first report, we confirmed that a test bench of CSEL resolved below 30 nm pattern over 0.2 um square area. Practical resolution of the system is limited by the chromatic aberration. We also demonstrated the CSEL system exposed deep sub-micron pattern over full-field for practical use. As an interim report of our development of MPEBDW system, we evaluated characteristics of the emitter array integrated with an active-matrix driving LSI on the CSEL system in this study. The results of its performance as an electron source for massively parallel operation are described. The CSEL as an experimental set consisted of the emitter array and a stage as a collector electrode that is parallel to the surface of the emitters. An accelerating voltage of about -5 kV was applied to the surface of the emitter array with respect to the collector. The target wafer and the emitter array were set between two magnets. The two magnets generated vertical magnetic field of 0.5 T to the surface of the target wafer. A gap between the emitter array and the target wafer was adjusted to a focus length depending on electron trajectories in the electromagnetic field in the system. The emitter array projected 100x100 electron beams with binary patterns and a dots image of its original size on the target wafer. The certain array was examined in order to evaluate the property of the e-beam exposure.