Masanori Nishiguchi

Precisional comparison of surface temperature measurement techniques for GaAs ICs

The accuracy of the three predominant techniques for measuring the surface temperatures of GaAs ICs under operation was investigated. The most important result is that the precision of commercially available computerized infrared microscopy is more limited than previously believed, especially in the case when the minimum IC element size is smaller than its spatial resolution. Some type of emissivity correction is necessary to obtain high precision. At this stage, therefore, the diode drop technique, an electrical method, and the transition point technique, a liquid crystal method, or their combination, must be used for measurement with high accuracy. The transition point technique has been determined to have a precision as great as +or-2 degrees C for measurement at the actual hot spot of non-sealed GaAs ICs. The diode drop technique is the only method which is useful for sealed ICs.<<ETX>>

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips

The authors investigate the reliability of mechanically ground chips through die-shear and thermal shock tests. The bonded chips, which were ground to 450 mu m thickness by an original technology, were proved to be as reliable as polished chips through 1000 cycles of thermal shock between -65 degrees C and +150 degrees C. No chip fracture occurred and no induced void was observed with scanning acoustic microscopy. The shear strength of the chips after thermal shocks remained at more than 10 kg, passing the MIL-STD-883C test. Surface flaws due to backgrinding, which would cause chip fracture, were eliminated by the slight chemical etching after backgrinding. Scrubbing action has been confirmed to be necessary to obtain void-free bondings consistently in low-cost production. The Sn in the Au-Sn preform easily forms on oxide film at the surface, which tends to prevent wetting at the bonding interface. This tin oxide film (300-400 AA) was observed through Auger electron spectroscopy (AES) to be broken down by scrubbing action. >

A Novel Truncated V-Groove 4H-SiC MOSFET with High Avalanche Breakdown Voltage and Low Specific on-Resistance

A breakdown of a conventional trench SiC-MOSFET is caused by oxide breakdown at the bottom of the trench. We have fabricated a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and the specific on-resistance of 3.5 mΩcm2.

Radiation tolerant GaAs MESFET with a highly-doped thin active layer grown by OMVPE

A novel GaAs MESFET structure with high radiation tolerance is proposed. Changes in electrical parameters of a GaAs MESFET as a function of total gamma -ray dose were found to be caused mainly by a decrease in the effective carrier concentration in an active layer. The structure was designed from a simulation based on an empirical relationship between the changes of the effective carrier concentration and the total gamma -ray dose. It was successfully demonstrated by utilizing a highly doped thin active layer (4*10/sup 18/ cm/sup -3/, 100 AA) grown by organometallic vapor-phase epitaxy (OMVPE). This MESFET can withstand a dose ten times higher (1*10/sup 9/ rads(GaAs)) than a conventional one can. >

High mechanical reliability of back-ground GaAs LSI chips with low thermal resistance

The fracture strength of mechanically ground GaAs LSI chips was investigated in comparison to that of chemically thinned ones to confirm their appropriateness for practical use in the GaAs LSI manufacturing process. In addition, the effect of wafer-thinning on thermal resistance was evaluated quantitatively. GaAs LSI-sized 6.35-mm-square chips with mirror-ground back-surfaces (R/sub max/=0.1 mu m) have been confirmed to be almost as highly reliable as chemically thinned ones through fracture stress experiments. The 1 mu m post-grinding chemical etching in the original wafer-thinning technology proved to be effective for eliminating the surface flaws due to grinding, which act as stress concentrators and reduce mechanical strength. The thermal resistance of background 5-mm-square GaAs chips was observed to be expectedly low utilizing the newly established surface temperature measurement technology based on the diode drop technique. Furthermore, the thermal resistance was judged to be independent of the back-surface treatment. >

Mechanical reliability effects of back-grinding upon GaAs LSI chips

The brittle damage layer of background GaAs LSI chips has been investigated through fracture toughness experiments, etching rate measurements, and SEM (scanning electron microscope) observations. The rough grinding damage which has a negative influence on the mechanical reliability of GaAs LSI chips penetrates to a 5-/spl mu/m depth on the finished surface. This is a little larger than than expected because the ductile damage layer due to rough grinding is only 0.6 /spl mu/m thick. However, this damage can be completely removed by 5-/spl mu/m mirror grinding and 1-/spl mu/m chemical etching, because the mirror grinding damage generates a 0.6-/spl mu/m-thick ductile deformation layer and a negligibly thin brittle deformation layer, which do not influence mechanical reliability.<<ETX>>

A multichip packaged GaAs 16*16 parallel multiplier

A GaAs 16*16 bit parallel multiplier utilizing multichip packaging technology is demonstrated. This multichip approach is undertaken in an effort to realize GaAs ULSIs with high yield and reliability, using multiple smaller scale integrated circuits. The device is composed of four GaAs 8*8 expandable parallel multipliers and a multichip package (MCP). The developed 8*8 b multipliers consist of 1097 E/D DCFL gates each and have a 2.4-ns multiplication time. The developed MCP is composed of five layers of alumina ceramic which include 50- Omega strip lines. The multiplication time of this 16*16 b multichip multiplier is 7.6 ns, and the total production yield is 70%. >