Masanori Uga

A fast and compact longest match prefix look-up method using pointer cache for very long network address

We propose a fast and compact longest match table look-up method for very long network addresses like IP version 6. This method uses two ideas for a routing-table arranged in a tree-structure. The first idea is to make table look-up fast by caching pointers to intermediate nodes in the tree, reducing the number of node traversals. The second idea is to reduce the memory size required for each node in the tree by one-third by eliminating common parts of addresses of adjacent nodes. Evaluating the performance of this method by using actual routing table data of an IP backbone network, we found it was five to ten times faster than a conventional method.

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.

On performance prediction of address lookup algorithms of IP routers through simulation and analysis techniques

Many address lookup methods on IP routers have been recently proposed to improve the packet forwarding capability; nevertheless, their performance prediction is very limited because of lack of consideration of actual traffic characteristics in their evaluations. It is necessary to consider actual traffic to predict more realistic performance in routers, especially in the case of layer 3 and 4 switches whose performance is more influenced by flow characteristics. In this paper, we propose new methods for predicting the routers performance based on the statistical analysis of the Internet traffic. We also present an example of its application to the existing table lookup algorithm, and show that simulation results based on our method can provide accurate performance prediction.

Performance prediction method for IP lookup algorithms

Many address lookup methods for use on IP routers to improve their packet-forwarding capability have been proposed. However, their performance prediction ability is poor because actual traffic characteristics are not considered in their evaluation processes. The actual traffic must be considered in order to predict router performance more accurately, especially for layer 3 and 4 address lookups, whose performances are more affected by the flow characteristics. We describe a method for predicting IP lookup algorithm performance that is based on statistical analysis of the Internet traffic. We present an example of its application to an existing IP lookup algorithm and show, based on simulation results, that our method can provide accurate performance prediction for IP lookup algorithms.

Design of IP+ATM switch router architecture for best-effort and guaranteed services in the next generation public data networks

This paper proposes IP+ATM switch router architecture for best-effort and guaranteed services for the next generation public data networks. The proposed architecture has advanced features: (1) scalable flow control, (2) scalable packet forwarding performance, (3) QoS control, and (4) a novel table lookup algorithm. Hardware-based high-speed IP packet forwarding engines and a sophisticated ATM switch are combined in the proposed architecture. Distributed packet forwarding engines are interconnected via the core ATM switching fabric, which employs a proprietary flow control mechanism. ATM traffic management and OAM capabilities are fully utilized to provide QoS guarantee for the label switch path (LSP). By combining the high-speed IP packet forwarding and sophisticated ATM LSP control mechanism, we can build the IP+ATM switch router.

Parallel packet forwarding architecture using ATM switch core for scalable performance

This paper proposes a label switch router architecture using ATM switch core. Hardware-based forwarding engines are attached to the switch core in a scalable fashion in the proposed label switch router. Dimensioning the number of forwarding engines is proposed to achieve scalable performance. An ATM virtual circuit is used as label switched path in the MPLS network. Traffic management and OAM capabilities are applied to achieve carrier-grade network control for the network infrastructure the next generation Internet is to provide.