Masaru Fukushi

Self-reconfigurable mesh array system on FPGA

Massively parallel computers consisting of thousands of processing elements are expected to be high-performance computers in the next decade. One of the major issues in designing massively parallel computers is the reconfiguration strategy in order to provide an efficient fault tolerance mechanism to avoid defective processors in such large scale systems. This paper develops a self-reconfigurable mechanism of mesh array for easy hardware implementation using local defect information. Compared to those of previous reconfigurable architectures, the proposed self-reconfigurable mechanism achieves almost the same system yields using only local defect information. A prototype of this self-reconfigurable array is implemented on FPGA and the hardware complexities are also discussed.

A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.

Fault tolerant multi-layer neural networks with GA training

This paper addresses a fault tolerant architecture of multi-layer neural networks with a genetic algorithm scheme. For large scale neural networks, implemented in a single chip or silicon wafer, it is necessary to develop self-recovery mechanisms that can automatically recover faults without a host computer. In this paper, we propose fault tolerant multi-layer neural networks employing both hardware redundancy and weight retraining in order to realise self-recovering neural networks. The main advantages of our architecture are low hardware cost for adding redundant neurons and fast training by a genetic algorithm implemented in hardware. A prototype system is implemented on a field programmable gate array to show the possibility of self-recovering neural networks.

A Job Scheduling Method Based on Expected Probability of Completion of Voting in Volunteer Computing

This paper addresses the problem of job scheduling in volunteer computing (VC) systems where each computation job is replicated and distributed to multiple participants (workers) to remove incorrect results. In the job scheduling of VC, the number of assigned workers to complete a job is an important factor for the system performance, however, it cannot be fixed because some of the workers may not return results in real VC. We propose a job scheduling method which considers the expected probability of completion (EPC) for each job based on the workers history information. The key idea of the proposed method is to assign jobs so that EPC is always greater than a specified value (SPC). By setting SPC as a reasonable value, any job in the proposed method can be completed without excess allocations, which leads to the higher performance of VC systems. Simulation results show that the performance of the proposed method is up to 5 times higher than that of the conventional method, while keeping the error rate lower than a required value.

Hierarchical Tori Connected Mesh Network

Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computers. A Hierarchical Tori connected Mesh Network (HTM) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-mesh networks that are hierarchically interconnected for higher-level networks. This paper addresses the architectural details of the HTM and explores aspects such as degree, diameter, cost, average distance, arc connectivity, bisection width, and wiring complexity. We also present a deadlock-free routing algorithm for the HTM using two virtual channels and evaluate the network’s dynamic communication performance using the proposed routing algorithm under uniform traffic and bit-flip traffic patterns. We evaluate the dynamic communication performance of HTM, H3DM, mesh, and torus networks by computer simulation. It is shown that the HTM possesses several attractive features, including constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, small wiring complexity, and high throughput per link and very low zero load latency, which provide better dynamic communication performance than that of H3DM, mesh, and torus networks.

Reconfiguration and Yield of a Hierarchical Torus Network

Abstract This paper presents the reconfiguration and yield of a new interconnection network, Hierarchical Torus Network (HTN). An HTN is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher level networks. The static network performance and dynamic communication performance under dimension-order routing of the HTN have already been studied and network performances are good. However, the fault tolerance performance of the HTN has not yet been evaluated. The goal of this paper is to derive a theoretical estimate of system yield for the HTN as a function of defect density with a reconfiguration approach by hardware redundancy. Yield is the probability of obtaining a fault-free network. Despite the dramatic improvement in fault tolerance in recent years, it is still necessary to provide redundancy and fault circumvention to achieve efficient system yield for large multicomputer systems. Thus, we provide redundant hardware to reconfigure the faulty nodes, switches, and links to healthy nodes, switches, and links. The results indicate that with a 25% redundancy the yield of the HTN is satisfactory. We also discuss the 3D-WSI implementation issue and show that HTN permits efficient VLSI/ULSI/WSI realization due to the fewer numbers of vertical links between the silicon wafers. The longest wire has a length of 4.5 cm, which represents 4.20 times improvement over the planar implementation.

A fault-tolerant routing method for 2D-mesh Network-on-Chips based on components of a router

Toward the realization of dependable high-end consumer electronics products, this paper proposes a fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs). Most of the existing routing methods regard the whole node (i.e. pair of a router and a core) as faulty; therefore, depending on the fault distribution, many fault-free nodes may become unusable (i.e. unused node) for proper packet routing. To overcome this problem, the proposed method routes packets based on a new fault model called partial fault model. The basic concept of the proposed method is to treat faults on the components of routers as the failure of routing functions. Simulation result shows that the proposed method reduces the number of unused nodes and improves communication latency up to 60% and 66%, respectively, compared with the exiting methods.

HTM: a new hierarchical interconnection network for future generation parallel computers

ABSTRACT In this paper, we have discussed the architectural structure, static network performance, and dynamic communication performance of a new hierarchical interconnection network called hierarchical Tori connected mesh network (HTM). For the exploration of static network performance, we have evaluated degree, diameter, cost, average distance, arc-connectivity, bisection width, and wiring complexity. We have also evaluated the dynamic communication performance of HTM, its counter rival H3DM, and conventional mesh and torus networks using a deadlock-free dimension order routing using two virtual channels under uniform and non-uniform traffic patterns. The dynamic communication performance is evaluated using computer simulation. We discovered that the HTM has a number of lucrative properties. These include constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, and less wiring complexity. HTM also yields high throughput per link and very low zero load latency, which provide better dynamic communication performance than that of H3DM, mesh, and torus networks.

A Dynamic Job Scheduling Method for Reliable and High-Performance Volunteer Computing

This paper proposes a dynamic job scheduling method for reliable and high-performance volunteer computing. In volunteer computing, each job is replicated and allocated to multiple participants (workers) to remove incorrect results by a voting mechanism. Hence, the number of workers necessary to complete a job is an important factor for the system performance; however, this is not well-considered in the existing methods. The proposed method defines the expected probability of completion for each job based on the workers secession probability. By allocating each job so that the expected probability is always greater than a specified value, the proposed method avoids excess job allocation, which leads to the higher performance. The performance of the proposed method is evaluated by computer simulation, under the two scenarios of workers having uniform and different processing speeds. It is found that the performance of the proposed method is higher than the existing method especially under the practical latter scenario.

Implementation of a Reliable Volunteer Computing System with Credibility-Based Voting

For the purpose of realizing highly-reliable volunteer computing (VC), this paper implements and evaluates a prototype VC system with credibility-based voting. The credibility-based voting is known as an efficient technique for eliminating incorrect calculation results. Although its theoretical performance has studied in detail and is shown to be better than a popular voting method, its real performance has not been evaluated yet. The implemented prototype VC system consists of a management server and a number of worker nodes. In the management server, each process including the credibility-based voting is multithreaded, and all information are managed in a database (DB). It is found by performance evaluations that the credibility-based voting is most time-consuming all processes and the main cause is DB access. It is also shown that the multithreading is effective to reduce the waiting time of the credibility-based voting, thus reducing the overall execution time of VC.