Masashi Takada

Criteria for Diagnosis of DIC Based on the Analysis of Clinical and Laboratory Findings in 345 DIC Patients Collected by the Research Committee on DIC in Japan

From analysis of the clinical and laboratory findings in the DIC patients collected by JRDC, diagnostic criteria for the diagnosis of DIC are proposed. The characteristics of the criteria are as follows: (1) a scoring system is adopted; (2) as the tests for scoring, PT, plasma Fbg level, serum FDP level, and platelet count are used; (3) different scores are given according to the grade of change in the results of the tests; (4) bleeding and clinical signs indicating organ dysfunction due to DIC are included in the scoring system; and (5) recognition of the well-known etiological factors of DIC is also scored.

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler

Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-Vt transistors. Since high-performance multiprocessor SoCs use leaky low-Vt transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high-performance embedded applications. We assign these 16 blocks to separate power domains so that they can be independently be powered off. A resume mode is also introduced where the power of the CPU is off and the user RAM is on for fast resume operation. An automatic parallelizing compiler schedules tasks for each CPU core and also performs power management for each CPU core. With the help of this compiler, each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing average operating power consumption. The compiler also executes power-off control of unnecessary CPU cores.

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS

The Role of Tissue Thromboplastin in the Development of DIC Accompanying Neoplastic Diseases

Procoagulant activity of gastric cancer tissues and leukocytes obtained from various types of leukemia have been studied with special reference to TTP. The following results were obtained. Homogenates of APL leukocytes and gastric cancer tissues contained strong procoagulant activities, most of which have been identified as TTP since the activities were neutralized by a specific antibody against purified human placenta TTP, inactivated by the removal of phospholipid with heptane-butanol mixture, and inactivated by the addition of phospholipase C. The delipidated homogenates regained procoagulant activities by relipidation procedures. These results also confirmed that TTP from APL leukocytes and gastric cancer tissues have the same lipoprotein properties as those of TTP in normal tissues. Though slight proteolytic activity and fibrinolytic activity were demonstrated in the homogenate of gastric cancer tissues, it was noted that the TTP activity was different from these two activities by partial purification of TTP from gastric cancer tissues. The TTP activity of 9 homogenates of gastric cancer tissues was 301 +/- 289 (mean +/- SD) units per mg protein, being higher in homogenates of mucinous adenocarcinoma and signet-ring cell carcinoma than in those of tubular and poorly differentiated adenocarcinoma. The mean TTP activity of leukocyte homogenates from 14 patients with APL and one out of 4 patients with CML in blastic crisis was 81 +/- 76 units/10(7) cells. The TTP activity of the homogenates of leukocytes from 7 out of 18 patients with AML and another patient with CML in blastic crisis ranged from one to six units/10(7) cells with a mean of 3.3 +/- 1.2. The TTP activity of leukocyte homogenates from the other 11 cases of AML, two cases of CML in blastic crisis, 6 cases of CML, and one case each of ALL and CLL were less than one unit/10(7) cells. In leukemic patients, all cases with a value of more than 202 for the product of units of TTP activity per 10(7) cells and differential count (%) of leukemic cells in the bone marrow smear (MU value) were accompanied by DIC. The MU value of leukemic patients correlated well to the plasma fibrinogen and serum FDP levels. All patients with a MU value of more than 277 died of DIC when a sufficient amount of heparin was not administered. On the other hand, no DIC developed in any of the patients with a MU value of less than 90.(ABSTRACT TRUNCATED AT 400 WORDS)

Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect

We have developed a 97.6 mm2 SoC that includes four SuperHtrade architecture CPUs and a DDR-2 controller with 90-nm CMOS for high-performance embedded applications. These four 600 MHz CPUs are identical and each has a floating point unit, 32/32 KB cache memory, and 152 KB local memory. CPUs totally achieve performance of 4320MIPS. Main on-chip 300 MHz 64-bit bus manages processors access and another dedicated connection holds cache coherency operation. Considering varying processing load, this chip targets both low power consumption (proportional to processing load), and constant on-chip bandwidth. Each processor can be operated different frequencies while keeping on-chip bus frequency constant. With utilizing this individual core clock distribution scheme, the following designs have been developed: (i) frequency transition control that permits on-chip bus access of other bus master, (11) light-sleep mode that maintains cache coherency control, (iii) cache snoop control logic that holds cache coherency between multiple frequency processors. The main on-chip interconnect (bus) connects four-processor and other on-chip IPs. The numbers of access master and access slave increase due to processor number. Standard-Vth (against high-Vth) cell usage and layout control achieved 300-MHz multi-master operation.

Performance and power evaluation of SH-X3 multicore system

We have developed an embedded processor that supports asymmetric multiple processor (AQMP), symmetric multiple processor (SMP), and an AMP/SMP hybrid system. It contains four SH-X3 cores used to support cache coherency from that obtained using an SH-X2 core. In this paper, we evaluate the following three techniques to improve the processing performance and reduce the power consumption in parallel processing in the processor. The first technique is snoop controller (SiNC) to improve cache coherency performance. The performance overhead by snoop is decreased up to 0.1% when SPLASH-2 is executed. The second technique is detection and resolution of synonym problems so that we may not use the page coloring for page table management. The processes handling time in Linux is reduced by 29.4% compared with the case solved the problem with software. The third technique is the individual core clock frequency and the light sleep mode which is used to maintain the cache coherency even when the cores are stopped, to reduce the power consumption. The energy is decreased by 5.2% and 4.5%, respectively. As a result, the SH-X3 core achieved a performance that has scalability proportional to 0.72-0.93 times the number of cores and a power saving of 4.5-44.0% without increasing the execution time.

Hardware support for resource partitioning in real-time embedded systems

Todays embedded systems require multiple functions such as real-time control and information technology and integrating these functions on a multi-core processor is one effective solution. However, this increases overhead as it is necessary to partition resources in this approach to protect them. We developed hardware support called ExVisor/XVS to reduce the overhead of partitioning resources to achieve real-time characteristics. This features a physical address management module (PAM) that uses direct address translation by using a single level page table based on an embedded systems memory usage. We evaluated the overhead in a virtual machines (VM) resource access through register transfer level (RTL) simulation and implementation on a field-programmable gate array (FPGA), and it was only less than 5.6% compared with the resource access time by a single core processor.