Masaya Tamamura
Fujitsu
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Featured researches published by Masaya Tamamura.
international solid-state circuits conference | 1992
Masaya Tamamura; S. Shiotsu; M. Hojo; K. Nomura; S. Emori; H. Ichikawa; T. Akai
The authors describe a 9.5-Gb/s Si bipolar ECL (emitter coupled logic) gate which has performance approximately equal to that of custom ICs because of optimized ECL circuit design, 0.3- mu m Si bipolar process, and 10-GHz package technology. 9.5-GHz operation is obtained with 1-mA switching current and 0.3*5.5 mu m/sup 2/ emitter area because emitter current density (J/sub e/) for shortest propagation time is 1.5 to 2.0 times as large as J/sub e/ for maximum f/sub T/. This ECL array was designed for multi-gigabit system operation and, in addition to digital, logic, and analog functions, it is easily configurable to provide high-speed functions such as clock distributors, shift registers, and ripple counters. >
Archive | 1998
Syouji Ohishi; Masaya Tamamura; Koichi Hatta
Archive | 1989
Masaya Tamamura; Shinji Emori; Yoshio Watanabe; Isao Shimotsuhama
Archive | 1996
Masaya Tamamura; Syouji Ohishi
Archive | 1989
Masaya Tamamura; Shinji Emori; Yoshio Watanabe; Isao Shimotsuhama
Archive | 1997
Shinichi Shiotsu; Masaya Tamamura
Archive | 1991
Masaya Tamamura; Yoshiro Morino
Archive | 1994
Masaya Tamamura; Shinichi Shiotsu
Archive | 1990
Masaya Tamamura; Shinji Emori
Archive | 1996
Masaya Tamamura; Syouji Ohishi