Masayuki Tomoyasu

Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si Cap and high-k metal gate stacks

We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO2 high-k gate dielectrics exhibited low C-V hysteresis (≪10 mV), interface trap density (7.5×1010), and gate leakage current (∼10−2A/cm2 at an EOT of 13.4Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of SiGe channels, which are major causes of the high off-state current of small bandgap energy SiGe pMOSFETs, by improving gate control over the channel.

High Mobility SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Epitaxially Grown on Si(100) Substrates with HfSiO2 High-k Dielectric and Metal Gate

High mobility metal–oxide–semiconductor field-effect transistors (MOSFETs) are demonstrated on strained or relaxed SiGe-on-Si heterostructures with Si cap/SiGe channel quantum well structures. Si cap processing is frequently used to enhance hole mobility of SiGe pMOSFETs by improving the interface quality of high-k gate dielectrics and SiGe channels. However, one of mechanisms that limits future gate oxide scaling is Ge enhanced Si oxidation, which results in a thick Si oxide interface layer. In this work, without using Si cap process, we have fabricated high mobility SiGe channel pMOSFETs after optimizing epitaxial SiGe-on-Si and high-k dielectric/metal gate process. High mobility with low off-state current have been achieved and correlated with epitaxial SiGe-on-Si processes.

Influence of Gas Chemistry and Ion Energy on Contact Resistance

Reactive ion etching (RIE) damage in contact hole etching is studied. The significant oxidation retardation layer (ORL) on Si surfaces is observed followed by high V pp (peak-to-peak voltage of 380 kHz RF) RIE. The depth of the ORL is linearly proportional to V pp, and it consists of a Si–C bond layer, according to X-ray photoelectron spectroscopy (XPS) analysis. The increase in contact resistance is found to be due to the existence of the ORL, using the sacrificial oxidation method and secondary ion mass spectroscopy (SIMS) analysis. The etch chemistries based on fluorocarbon-containing gas mixtures are characterized in terms of contact resistance and ORL. When hydride-containing gas mixtures are used in RIE, the contact resistance is low and the ORL depth is small. When CO-containing gas mixtures are used, the contact resistance is high and ORL depth is large. These different properties result from the different amounts of carbon implanted at the silicon surface.

Fabrication of segmented-channel MOSFETs for reduced short-channel effects

To facilitate continued CMOS technology scaling, thin-body transistor structures such as the FinFET [1] and fully depleted silicon-on-insulator (FD-SOI) MOSFET [2] have been proposed to better suppress short-channel effects (SCE) than the conventional MOSFET structure in the sub-25 nm gate length (Lg) regime. However, these structures require either more challenging fabrication processes or more expensive silicon-on-insulator substrates. Recently, a segmented-channel bulk MOSFET (SegFET) structure [3] was proposed as a more evolutionary solution that offers the advantages of a thin-body MOSFET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).