Massimo Baleani

Fault-tolerant platforms for automotive safety-critical applications

Fault-tolerant electronic sub-systems are becoming a standard requirement in the automotive industrial sector as electronics becomes pervasive in present cars. We address the issue of fault tolerant chip architectures for automotive applications. We begin by reviewing fault-tolerant architectures commonly used in other industrial domains where fault-tolerant electronics has been a must for a number of years, e.g., the aircraft manufacturing industrial sector. We then proceed to investigate how these architecture could be implemented on a single chip and we compare them with a metric that combines traditional terms such as cost, performance and fault coverage with flexibility, i.e. the ability of adapting to changing requirements and capturing a wide range of applications, an emerging criterion for platform design. Finally, we describe in some details a cost effective dual lock-step platform that can be used as a single fail-operational unit or as two fail-silent channels trading fault-tolerance for performance.

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The HW/SW codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (extended finite state machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementations that best utilize this architecture. Encouraging preliminary results are shown for automotive electronic control examples.

Efficient embedded software design with synchronous models

Model-based design is an important approach for embedded software. The method starts from a mathematical representation of the design problem and derives the software implementation from this representation. The model that has had most success especially for control dominated application is synchronous reactive. While this model simplifies the way of dealing with concurrency by decoupling functional and timing aspects, when implemented, it may be inefficient since the synchronous assumption implies constraints that are stronger than needed. We present in this paper a method for improving the efficiency of the software design process, by relaxing computation constraints, while preserving the synchronous computation semantics, with the introduction of a particular inter-task communication mechanism. We show how this mechanism can be implemented on single processor, multi processor and distributed implementation platforms.

Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development

Embedded software design for real time reactive systems has become the bottleneck in their market introduction into complex products such as automobiles, airplanes, and industrial control plant. In particular, functional correctness and reactive performance are increasingly difficult to verify. The advent of model-based design methodologies has alleviated some of the verification-related problems by making the code-generation process flow automatically from the model description. Given the relative infancy of this approach, several companies rely upon design flows based on different tools connected together by file transfer. This way of integrating tools defeats the very purpose of the methodology, introducing a high potential of errors in the transformation from one format to another and preventing formal analysis of the properties of the design. We propose to adopt a formal transformation across different tools and we give an example of this approach by linking two tools that are widely used in the automotive domain, Simulink and ASCET. We believe that this approach can be applied to any embedded software design flow to leverage the power of all the tools in the flow.

HW/SW codesign of an engine management system

The design process for an engine management system is presented. The functional specification of the system has been captured using C and C++ as specification languages. The validation of the specification has been carried out using functional simulation. Then an architecture for the implementation of the functional specification is selected among a set of three possible alternatives, all based on the same micro-controller; characterized by different hardware-software trade-offs. The choice is motivated by a fast performance estimation that can also be used to identify the parts of the design that could be moved across the hardware-software partition to obtain better cost or better performance. The case study has been performed in the Felix VCC framework.

Semantics-Preserving Design of Embedded Control Software from Synchronous Models

The design of embedded controllers is experiencing a growth in complexity as embedded systems increase their functionality while they become ubiquitous in electronic appliances, cars, airplanes, etc. As requirements become more challenging, mathematical models gain importance for mastering complexity. Among the different computational models proposed, synchronous models have proved to be the most widely used for control dominated applications. While synchronous models simplify the way of dealing with concurrency by decoupling functional and timing aspects, their software implementation on multitasking and multiprocessor platforms is far from straightforward, because of the asynchronous nature of most industrial software platforms. Known solutions in the literature either restrict the solution space or focus on special cases. We present a method for preserving the synchronous semantics through buffer-based intertask communication mechanisms, grounded on an abstraction of the target platform. This allows us to deal with any task set and, most importantly, being independent of the implementation, to explore the design space effectively.

Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard

Fast design and verification is becoming a necessity for electronic industry to hit the more and more restrictive market requests. The model-based approach represents a possible way to ensure fast and flexible system design and verification, allowing a quantitative exploration of the space of solutions. In this paper the SystemC environment has been used to design a complete TLM model of IEEE 802.15.4 standard. The TLM abstraction level design allows high simulation speed, high-level performance analysis and an easy evaluation of a large set of performance parameters.

Uniprocessor scheduling under precedence constraints for embedded systems design

In this paper, we present a novel approach to the constrained scheduling problem, while addressing a more general class of constraints that arise from the timing requirements on real-time embedded controllers. We provide general necessary and sufficient conditions for scheduling under precedence constraints and derive sufficient conditions for two well-known scheduling policies. We define mathematical problems that provide optimum priority and deadline assignments, while ensuring both precedence constraints and systems schedulability. We show how these problems can be relaxed to corresponding integer linear programming (ILP) formulations leveraging on available solvers. The results are demonstrated on a real design case.

Multi Processor Micro-Controllers for Automotive Safety-Critical Applications

Abstract Fault-tolerant electronic sub-systems are becoming a standard requirement as electronics becomes more and more pervasive in present cars. To master the increasing complexity of these devices a new design flow has to be put in place, which enables a tight interaction among system companies and system integrators. In this paper we present multi-processor micro-controller architectures devised within the Platform-Based Design framework to address fault-tolerant automotive applications.

An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms

The increasing complexity of embedded systems and demands for quicker turn-around times require reuse of hardware and software components. Reconfigurable hardware technology opens a new implementation space where software and hardware design cycles might be very close in time and where a broader range of applications can be mapped on. The exploitation of reconfigurable platforms is often hampered by the lack of a unified software/(reconfigurable) hardware design flow. In this paper, we presented an enhancement of the POLIS framework for fast exploration and implementation of input-output subsystems on configurable systems-on-chip (CSoCs). The designer, given the functionality of the system described in POLIS, explores different solutions at the co-design level. Those solutions that, based on the estimation of performances, violate the timing requirements are pruned without the need of any FPGA synthesis and validation steps. The explored solutions satisfying the constraints are then implemented. The automatic generation of the hardware description and the hardware-software interface make the implementation step extremely fast leading to very short system design cycles.