Massimo Maresca

Connection autonomy in SIMD computers: a VLSI implementation

Abstract Fine-grain SIMD (single instruction stream-multiple data stream) parallel architectures exhibit very high performance in a variety of application fields (such as vision, scientific computing, geometric modeling, and artificial intelligence) mainly because of the massive data parallelism. It is, however, desirable to increase the autonomy of the SIMD architecture for further efficiency. For example, with operation autonomy different processors are able to execute different operations, while with address autonomy , each processor can fetch data from memory locations different from the other processors. Because of the quantity (i.e., tens of thousands) and the simplicity (e.g., bit-serial) of the processors in fine-grain SIMD system, these autonomies may be too expensive to justify their benefits. Nevertheless, one type of autonomy, connection autonomy , is extremely beneficial and is economic in VLSI implementation. We investigate connection autonomy for fine-grain SIMD parallel architecture in this paper by showing a model for connection autonomy, the utilization of connection autonomy, and its VLSI implementation. The architecture and the instruction set of the YUPPIE system (Yorktown ultra parallel polymorphic image engine) are presented and some programming examples are given. We show that, by adding 20% silicon area over each processor, connection autonomy can deliver orders of magnitude of performance improvement over the same network without connection autonomy.

Image processing on high-performance RISC systems

The recent progress of RISC technology has led to the feeling that a significant percentage of image processing applications, which in the past required the use of special purpose computer architectures or of ad hoc hardware, can now be implemented in software on low cost general purpose platforms. We decided to undertake the study described in this paper to understand the extent to which this feeling corresponds to reality. We selected a set of reference RISC-based systems to represent RISC technology, and identified a set of basic image processing tasks to represent the image processing domain. We measured the performance and studied the behavior of the reference systems in the execution of the basic image processing tasks by running a number of experiments based on different program organizations. The results of these experiments are summarized in a table, which can be used by image processing application designers to evaluate whether RISC-based platforms are able to deliver the computing power required for a specific application.

Parallel implementation of the full search block matching algorithm for motion estimation

Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H.261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires the use of special purpose architectures to obtain real-time performance. We propose an approach to the parallel implementation of the Full Search Block Matching Algorithm which is suitable for implementation on massively parallel architectures ranging from large scale SIMD computers to dedicated processor arrays realized in ASICs. While the first alternative can be used for the implementation of high performance coders the second alternative is particularly attractive for low cost video compression devices. This paper describes the approach proposed for the parallel implementation of the Full Search Block Matching Algorithm and the implementation of such an approach in an ASIC.

Internet protocol support for telephony

In this paper, we consider the evolution of telephone networks from time-division multiplexing circuit switching to packet switching and, in particular, to packet switching-based on Internet Protocol (IP-supported telephony). We analyze IP-supported telephony design solutions by proposing a layered reference model in which each layer is associated to a subset of the functions that support telephony. We use the reference model to establish a terminology and a framework for the comparison of the design solutions. We group the design solutions in scenarios and compare them in terms of the reference model proposed. We then focus on IP telephony, in which IP is used in telephone company networks, and on Internet telephony, in which the Internet is used to support telephony. We show that they both can be seen as implementations of the same architecture, which consists of a set of components, associated to functions, and of the interactions among these components. We then consider the issue of voice-data integration and analyze the variety of design solutions that can be adopted to integrate voice and data.

VISIONS: A Service Oriented Architecture for Remote Vehicle Inspection

This paper presents a system for remote vehicle inspection developed within the VISIONS (vehicular system interface for open network service) research project funded by the European Commission. The system architecture allows digital service exchange between vehicles and road infrastructures (e.g., road, tunnel, terminal containers) and makes available a large set of significant vehicle data (e.g., engine status, tire pressure, cargo documents) directly to the infrastructure information system applications. The VISIONS system, based on the service oriented architecture, includes appropriate extensions to such an architecture to meet domain-specific requirements such as highly dynamic event handling and short service persistence in the network. The paper describes the architecture, the system prototype and the experimental results obtained in a pilot system located in the Mont Blanc Tunnel

A Platform for Smart Object Virtualization and Composition

One of the most challenging objectives of the Internet of Things (IoT) domain is the identification of interaction paradigms and communication standards to integrate smart objects (SOs), i.e., physical objects able to interact with the network. Such interaction paradigms and communication protocols belong to what can be called the IoT application layer, on which this paper focuses. This paper presents app execution platform (AEP), a platform that supports the design, deployment, execution, and management of IoT applications in the domain of smart home, smart car, and smart city. AEP was designed to coherently fulfill a set of requirements covered only partially or in a fragmented way by other IoT application platforms. AEP focuses on SO virtualization and on composite application (CA) orchestration and supports dynamic object availability.

An Architecture for a Mashup Container in Virtualized Environments

This paper presents the architecture and the organization of a Mashup Container that supports the deployment and the execution of Event Driven Mashups (i.e., Composite Services in which the Services interact through events rather than through the classical Call-Response paradigm) following the Platform as a Service model in the Cloud Computing paradigm. We describe the two main modules of the container, namely the Deployment Module and the Service Execution Platform, and focus our attention on the performance on of the latter. In particular we discuss the results of an evaluation test that we run in a virtualized environment (VMware based) supporting scalability and fault tolerance.

An execution platform for event driven mashups

This paper presents a Service Execution Platform for Event Driven service compositions (a.k.a. Mashups), typically used in Telco services, and more in general applicable in domains characterized by a working principle based on asynchronous events. The platform reference model is based on an orchestration system and on a set of service proxies hosted in the Service Execution Platform. The orchestration system executes Mashup sessions, i.e., instances of service compositions activated by external events, by coordinating the actions of the service proxies and takes care of load balancing, security (AAA), and fault tolerance. The paper presents the software architecture of the platform and shows how Web Service technology can be used to support event based communication and how session-less orchestration provides support for scalability and fault tolerance. Finally the paper presents a prototype implementation of the platform and a set of experimental results.

Hardware Support for Fast Reconfigurability in Progress Arrays

Massively parallel computers are implemented by means of modules at different packaging levels. This paper discusses a hierarchical node clustering scheme (HNC) for packaging a class of reconfigurable processor arrays called Polymorphic Processor Array (PPA) which uses circuit-switchingbased routers at each node to deliver a different topology at every instruction. The PPA family suffers from an unknown signal delay between arbitrary two nodes connected by the circuited-switched paths. This either forces the hardware clock to compromise to the worst signal delay or makes the software dependent on the system size. The use of the HNC scheme allows to obtain communication speed-up and automatic control, at the compiler level, over signal propagation delay.

Parallel computer vision on Polymorphic Torus architecture

Polymorphic Torus is a novel interconnection network for SIMD massively parallel computers, able to support effectively both local and global communication. Thanks to this characteristic, Polymorphic Torus is highly suitable for computer vision applications, since vision involves local communication at the low-level stage and global communication at the intermediate- and high-level stages. In this paper we evaluate the performance of Polymorphic Torus in the computer vision domain. We consider a set of basic vision tasks, namely,convolution, histogramming, connected component labeling, Hough transform, extreme point identification, diameter computation, andvisibility, and show how they can take advantage of the Polymorphic Torus communication capabilities. For each basic vision task we propose a Polymorphic Torus parallel algorithm, give its computational complexity, and compare such a complexity with the complexity of the same task inmesh, tree, pyramid, and hypercube interconnection networks. In spite of the fact that Polymorphic Torus has the same wiring complexity as mesh, the comparison shows that in all of the vision tasks under examination it achieves complexity lower than or at most equal to hypercube, which is the most powerful among the interconnection networks considered.