Massimo V. Fischetti

Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys

Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...

Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering

The high dielectric constant of insulators currently investigated as alternatives to SiO2 in metal–oxide–semiconductor structures is due to their large ionic polarizability. This is usually accompanied by the presence of soft optical phonons. We show that the long-range dipole field associated with the interface excitations resulting from these modes and from their coupling with surface plasmons, while small in the case of SiO2, for most high-κ materials causes a reduction of the effective electron mobility in the inversion layer of the Si substrate. We study the dispersion of the interfacial coupled phonon-plasmon modes, their electron-scattering strength, and their effect on the electron mobility for Si-gate structures employing films of SiO2, Al2O3, AlN, ZrO2, HfO2, and ZrSiO4 for “SiO2-equivalent” thicknesses ranging from 5 to 0.5 nm.

Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures. I. Homogeneous transport

Monte Carlo simulations of electron transport in seven semiconductors of the diamond and zinc-blende structure (Ge, Si, GaAs, InP, AlAs, InAs, GaP) and some of their alloys (Al/sub x/Ga/sub 1-x/As, In/sub x/Ga/sub 1-x/As, Ga/sub x/In/sub 1-x/P) and hole transport in Si were performed at two lattice temperatures (77 and 300 K). The model uses band structures obtained from local empirical pseudopotential calculations and particle-lattice scattering rates computed from the Fermi golden rule to account for band-structure effects. Intervalley deformation potentials significantly lower than those which have been previously reported are needed to reproduce available experimental data. This is attributed to the more complicated band structures, particularly around the L- and X-symmetry points in most materials. Satisfactory agreement is obtained between Monte Carlo results and some experiments. >

Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

A six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer. Scattering assisted by phonons and surface roughness has been accounted for, also comparing a full anisotropic model to an approximated isotropic treatment of the matrix elements. Satisfactory qualitative (and in several cases also quantitative) agreement is found between experimental data and theoretical results for the density and temperature dependence of the mobility for (001) surfaces, as well as for the dependence of the mobility on surface orientation [for the (011) and (111) surfaces]. Both compressive and tensile strain are found to enhance the mobility, while confinement effects result in a reduced hole mobility for a Si thickness ranging from 30 to 3 nm.

Silicon CMOS devices beyond scaling

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks

An experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to SiO2 charge trapping models with one exception. Unlike SiO2 models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density (Ninj) in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and Ninj, thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the...

Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity

We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrodinger and Poisson equations. A rigorous surface roughness scattering model is derived, which takes into account the roughness-induced fluctuation of the subband wave function, of the electron charge, and of the interface polarization charge. Dielectric screening of the scattering potential is modeled within the random phase approximation, wherein a generalized dielectric function for a multi-subband quasi-one-dimensional electron gas system is derived accounting for the presence of the gate electrode and the mismatch of the dielectric constant between the semiconductor and gate insulator. A nonparabolic correction method is also presented, which is applied to the calculation of the density of states, the matrix element of the scattering potential, and the generalized Lindhard function. The Coulomb scattering due to the fixed i...

On the enhanced electron mobility in strained-silicon inversion layers

The recently reported large enhancement of the electron mobility in strained-Si inversion layers at large carrier concentrations cannot be easily explained: The strong carrier confinement in inversion layers removes the sixfold degeneracy of the conduction-band minima, much as tensile in-plane strain does, so that the effect of strain should become irrelevant at large sheet carrier densities. The problem is studied by calculating the electron mobility accounting for scattering with phonons and interface roughness. Surprisingly, the latter process is found to be significantly stronger in strained layers for a given interface roughness. Only the ad hoc assumption of increasingly smoother interfaces with increasing strain seems to explain the data.

Understanding hot‐electron transport in silicon devices: Is there a shortcut?

Results of a Monte Carlo study of carrier multiplication in silicon bipolar and field‐effect transistors and of electron injection into silicon dioxide are presented. Qualitative and, in most cases, quantitative agreement is obtained only by accounting for the correct band structure, all relevant scattering processes (phonons, Coulomb, impact ionization), and the highly nonlocal properties of electron transport in small silicon devices. In addition, it is shown that quantization effects in inversion layers cause a shift of the threshold energy for impact ionization which is very significant for the calculation of the substrate current in field‐effect transistors. Conservation of parallel momentum, image‐force corrections, dynamic screening of the interparticle Coulomb interaction, and improvements to the WKB approximation are necessary to treat correctly the injection of electrons from silicon into silicon dioxide. The validity of models—analytic or Monte Carlo—which treat hot‐electron transport with oversimplified physical approximations is argued against. In a few words, there is no shortcut.

Hybrid-orientation technology (HOT): opportunities and challenges

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.