Matthew A. Pace

Scientific/industrial camera-on-a-chip using Active Column Sensor CMOS imager core

The first section will review the requirements for scientific/industrial cameras and discuss the limitations of conventional CCD and active pixel sensors (APS) approaches. The next section will describe the Active Column Sensor technology, and discuss the reasons for the improved performance compared to passive pixel CMOS and APS imagers. Then the Active Column SensorTM (ACS) pixel structure and modes of pixel operation will be discussed. The paper will also describe the other camera functions that are placed on the same substrate. Experimental results including images will be presented. The paper will close with a glimpse into the future of industrial and scientific CMOS ACS image enabled systems.

Megarad and scientific CIDs

Nine imagers that exploit distinctive CID properties and incorporate on-chip amplifier configurations (including preamplifier/pixel) were developed for use in automation, nuclear and scientific applications. TV compatible (11 mm) formats of 768H X 575V (European) and 755H X 484V (domestic-RS170) were fabricated for radiation- hardened product cameras. Operating CIDs provided excellent signal-to-noise at radiation levels of 106 rads/hr, and accumulated dose beyond 106 rads in silicon (60Co source). Large format imagers featuring random pixel and subarray addressability, were created for spectroscopy and other scientific applications. They possess a 27 X 27 micrometers 2 pixel in 1024H X 1024V, 1024H X 256V, and 512H X 512V formats. Pixels and subarrays (even overlapping subarrays) can be read out destructively or non-destructively. The above features can be combined with 2D on- CID pixel binning because CID binning preserves the spatial fidelity of the pixel charge. Two 1024 linear-type imagers were fabricated with a preamplifier-per-pixel structure and a 27 X 150 micrometers 2 large capacity photo-site. One device features on-chip large signal differencing capability between successive exposures. Two 512H X 512V (20 X 20 micrometers 2 pixel) format imagers were created for UV photon-counting applications. The imagers provide high local count rates through video-rate random subarray addressability and subarray charge injection.

1.5-FET-per-pixel standard CMOS active column sensor

This paper describes a new improved method of employing an amplifier per pixel that eliminates FET threshold and gain variations problems of prior art. Existing amplifier per pixel designs utilizes 3 or 4 FETs per pixel and the amplifier consists of a source follower. The source follower is problematic in 2D arrays due to threshold variations and resulting gain variations per pixel causing extensive peripheral circuitry and/or software to correct. The active column sensor employs a true unity gain amplifier per pixel, eliminating threshold and gain variations. The simplified pixel electronics allow for smaller and/or more sensitive pixels and always at lower cost through improved yields. Disclosure of 1.5 FET double poly, 1.5 FET single poly, and photodiode configurations and with result on various pixels.

Radiation tolerant CID imager

A new European-format CID imager with improved radiation tolerance was developed to meet the operational requirements of the burgeoning international nuclear power generation and waste management markets. Incorporating an inherently radiation tolerant CID architecture fabricated using a new improved radiation resistant process, the imager is designed to survive total dose radiation of more than 106 rads (gamma-Sl) in environments greater than 105 rads/hr (gamma-Sl). The imager format is 786 pixels/row by 612 rows mapped into an 11 MM diagonal optical format. The device incorporates an 11.5 micron2 pixel structure that can be read out either in an interlaced CCIR TV compatible or progressive 25 Hz mode. Additionally, the imager incorporates a deep depletion high resistivity structure that makes it suitable for sensing x ray, nuclear as well as E-beam forms of radiation. The CID device design and tooling was completed during 1993. Sample devices were fabricated and tested during late 1993 and early 1994. Preliminary test results together with further imager and camera development plans are included herein.

Scientific CMOS CID imagers

A new family of binary format CMOS CID imagers was designed to meet the random pixel addressing and on-chip signal manipulation requirements of may scientific applications. Key features include true random pixel and programmable subarray addressing, non-destructive readout and charge injection (clearing) that eliminate the need to read out superfluous pixels. And, programmable horizontal/vertical binning provides improved signal/noise and permits spatial signal consolidation even when reading out overlapping subarrays. The imagers incorporate on-chip preamplifiers for low noise readout. Inherent CID pixel characteristics such as non-destructive, non-blooming read-out that permit adaptive exposure control and linear dynamic range extension are maintained. Formats include 10242, 5122, and 1024 X 256. All incorporate 27.0 micron contiguous square pixels with in excess of 106 electron well capacity. Serial horizontal and vertical input ports are provided to accept the coordinates of the pixel or subarray to be readout. Rapid subarray readout is facilitated via a single pixel advance clock that is used in conjunction with each random access decoder. A description of the architecture, imager operation and application will be presented.

Selectable one-to-four-port, very high speed 512 x 512 charge-injection device

A high-speed 512 X 512 charge injection device with selectable one to four video ports has been developed, fabricated, and tested beyond the designed speed of operation. The imager has four independently controllable video ports allowing for all possible combinations. This is accomplished by having each port hard wired to one out of every four rows sequentially. Each port is selected via a multiplexer in the sequence desired. The horizontal scanner was designed to operate up to 30 MHz. The device was tested at the wafer level to 42 Mhz element rate per port. This element rate allows a maximum of 168 MHz element rate with four ports operating in parallel.

Ultrahigh-speed CMOS scanning linear imager family

A family of monochrome, high-speed linear imagers has been developed with each device to be available as a single chip fabricated using a standard commercially available CMOS process. Currently, the 2048 pixel device has been fabricated using a 0.5-micron CMOS process and its architecture, functionality and performance is described. The family of imagers features a unique combination of high functional integration, very high speed, low dark current, high sensitivity and high pixel-to-pixel uniformity. The pixels are 7.0 microns by 7.0 microns and have 100 percent fill factor. The high pixel-pixel uniformity is made possible by using low dark current pixels, a correlated double sampler circuit per pixel and a fully differential video bus. High functional integration is enabled by on-chip logic that is provided to minimize support circuitry and simplify application. Included are several exposure modes that provide full-frame electronic shutter, independent control of integration time and simultaneous integration and read-out. Only 5 volts DC and clock signal running at twice the desired pixel rate are required for basic operation. Low dark current and high sensitivity result from a novel pixel and low-noise preamplifier structure. A novel video multiplexing structure provides the very high read-out speed of 60 Mpixel/sec per 2048 pixel segment while sustaining an MTF of 50 percent at 35 line pairs per millimeter.