Matthew R. Miller

A background calibration technique for multibit delta-sigma modulators

To achieve high resolution in current IC fabrication processes, multibit delta-sigma modulators incorporate either dynamic element matching (DEM) or calibration techniques to overcome the mismatch of the feedback DAC elements. This paper presents a new background calibration technique for multibit delta-sigma modulators. The proposed technique works by modulating each DAC element in turn with an out-of-band digital sequence and digitally measuring the magnitude of the resulting spectral components. The output of the modulator is then digitally corrected using the results of the calibration measurement. Because the calibration tones are added out of band, the system operates without interrupting the normal ADC function of the modulator.

A multi-bit sigma-delta ADC for multi-mode receivers

A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.