Matthias Bucher

An efficient parameter extraction methodology for the EKV MOST model

This paper presents a new parameter extraction methodology, based on an accurate and continuous MOS model dedicated to low-voltage and low-current analog circuit design and simulation (EKV MOST Model). The extraction procedure provides the key parameters from the pinch-off versus gate voltage characteristic, measured at constant current from a device biased in moderate inversion. Unique parameter sets, suitable for statistical analysis, describe the device behavior in all operating regions and over all device geometries. This efficient and simple method is shown to be accurate for both submicron bulk CMOS and fully depleted SOI technologies.

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

Abstract In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

Design-oriented characterization of CMOS over the continuum of inversion level and channel length

A methodology for small signal characterization of CMOS processes over the full range of inversion level and channel length is presented. Measured transconductance and output conductance of a 0.5 /spl mu/m standard CMOS process are presented from deep weak inversion to deep strong inversion for both NMOS and PMOS devices for channel lengths ranging from 0.5 /spl mu/m to 33.4 /spl mu/m. The data is presented in normalized form permitting device evaluation at any inversion level, channel length, and drain current. This characterization is useful for modern analog CMOS design anywhere in the continuum of inversion level and channel length. This method furthermore presents a novel and rigorous benchmark for evaluating the accuracy of compact MOS models. Initial results are given illustrating EKV MOS model transconductance accuracy. The characterization methodology can be extended to deeper submicron processes addressing the increasing uncertainty in small signal parameter values and MOS model accuracy.

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation

Abstract Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.

Estimating key parameters in the EKV MOST model for analogue design and simulation

Recent availability of the public-domain EKV (Enz-Krummenacher-Vittoz) MOST model from EPFL in a number of circuit simulators facilitates the intuitive design, analysis and simulation of analogue and mixed-mode circuits and systems exploring the numerous modes of operation of the MOST, particularly at low-voltage (LV) and low-current (LC). A practical approach for either extracting the most critical parameters and/or adapting those already available from widely used SPICE models (levels 2 and 3) for use with the EKV model is presented and opportunities for engineering education are considered. The effectiveness of the approach is illustrated by measured results from CMOS and BiCMOS technologies.

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Analog/RF performance of double-gate MOSFETs in the sub-20-nm regime is investigated using ATLAS device simulator. It is shown that graded channel dual material double gate (GCDMDG) achieves higher drain current, peak transconductance, and higher values of cutoff frequency at lower drain currents. This novel architecture also provides better intrinsic gain for an amplifier. A new analog/RF figure of merit, gain transconductance frequency product (GTFP) is proposed that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The peak GTFP is observed at the higher end of moderate inversion, slightly above threshold. The GCDMDG device outperforms in terms of GTFP and is more favorable for shorter channel length devices.

Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.

Accurate MOS modelling for analog circuit simulation using the EKV model

Effective, manufacture-oriented design and simulation of high-performance analog and mixed-mode integrated circuits and systems is known to critically depend on the quality of extracted device parameters as well as the simulation model being used. This has gained increased relevance for low-voltage low-current designs, either in bulk CMOS or emerging SOI technologies. The EKV model is introduced within a complete, statistically efficient and simple characterisation methodology. Valuable insight into the behavior of transistors in strong, moderate and weak inversion is gained, which also allows for increased design creativity. Measured results from a submicron bulk CMOS and a fully depleted SOI process illustrate the accuracy of the EKV model and the associated parameter extraction under several geometries and regions of device operation.