Matthias Rudolph

Evaluation of an advanced dual hard mask stack for high resolution pattern transfer

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO2 and ZrO2 hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO2 based materials were investigated with focus on surface roughness reduction since it influences the final line etch roughness. Here Si-doped ZrO2 (ALD) and spin-coatable ZrO2 were compared to the pure and crystalline ZrO2 as main selective material.

High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures

This paper focuses on zirconia and TiN based metal-isolator-metal capacitors integrated in immediate vicinity to the Si substrate. A high capacitance density is aimed by significant area enhancement realized through silicon pattering. By material optimization the capacitors also withstand higher supply voltages and show excellent temperature and reliability performance independently of the 3D structure.

Feasibility study of optical/e-beam complementary lithography

Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at 193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho- Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional (1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data prep efforts such as layout splitting. In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements necessary for this mix & match approach will be discussed.

Evaluation of water based intelligent fluids for resist stripping in single wafer cleaning tools

The application of phasefluid based intelligent fluids® in the field of photoresist stripping was studied. Due to their highly dynamic inner structure, phasefluids penetrate into the polymer network of photoresists and small gaps between resist layer and substrate and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their efficiency in various resist stripping applications including initial results on copper metallization. Furthermore intelligent fluids® have been evaluated on an industry standard high volume single wafer cleaner. A baseline process on 300 mm wafers has been developed and characterized in terms of metallic and ionic impurities and defect level. Finally a general proof of concept for removal of positive tone resist from 300 mm silicon wafers is demonstrated.

Patterning and imaging with electrons: assessing multi-beam SEM for e-beam structured CMOS samples

Electron optics can assist in the fabrication of semiconductor devices in many challenges that arise from the ongoing decrease of structure size. Examples are augmenting optical lithography by electron beam direct write strategies and high-throughput imaging of patterned structures with multiple beam electron microscopes. We use multiple beam electron microscopy to image semiconductor wafers processed by electron beam lithography.

Introduction of an innovative water based photoresist stripping process using intelligent fluids

The usage of phasefluid based stripping agents to remove photoresists from silicon substrates was studied. Due to their highly dynamic inner structure phasefluids offer a new working principle, they are penetrating layers through smallest openings and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their cleaning efficiency as well as contamination behavior to enable usage in semiconductor and MEMS manufacturing. A general proof of concept for the usage of phasefluids in resist stripping processes is shown on silicon coupons and BKM’s are given for different resist types. In addition a baseline process on 12inch wafers has been developed and characterized in terms of metallic and ionic impurities and defect level.

Innovative and water based stripping approach for thick and bulk photoresists

The usage of phase fluid based stripping agents to remove photoresists from silicon substrates was studied. Photoresists are required for many silicon based technologies such as MEMS patterning, 3D-Integration or frontend and backend of line semiconductor applications [1]. Although the use of resists is very common, their successful integration often depends on the ability to remove the resist after certain processing steps. On the one hand the resist is changing during subsequent process steps that can cause a thermally activated cross-linking which increases the stripping complexity. Resist removal is also challenging after the formation of a hard polymer surface layer during plasma or implant processes which is called skin or crust [2]. On the other hand the choice of stripping chemistry is often limited due to the presence of functional materials such as metals which can be damaged by aggressive stripping chemistries [3].

Scaling and optimization of high-density integrated Si-capacitors

This paper focuses on the scaling and optimization of metal-isolator-metal capacitors integrated in 3D Si structures. Scaling to high capacitance density is aimed by the use of high-k dielectrics and a significant area enhancement realized through silicon pattering with increasing aspect ratios. By material and process optimization the capacitors show excellent IV and CV characteristics with high temperature and reliability performance independently of the 3D structure. A fully functional capacitor of 4mm2 consisting of 80 Mil trenches with an overall capacitance of 850nF can be demonstrated.