Mattias O'Nils

Exploration of target architecture for a wireless camera based sensor node

The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable.

Operating system sensitive device driver synthesis from implementation independent protocol specification

We present a method for generation of the software part of a HW/SW interface (i.e. the device drivers), which separates the behaviour of the interface from the architecture dependent parts. We do this by modelling the behaviour in ProGram (a grammar based protocol specification language) and capture the processor and OS kernel parts in separate libraries. By separating the behaviour from the architectural specific parts, compared to other approaches up to 50% development time can be saved the first time the component is used, and up to 98% for each time the interfaced component is reused.

Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications

We have separated the information requiredfor HW/SW interface synthesis into three parts,the protocol specification, the operating system related information,and the processor related information. From these inputs a synthesistool generates (a) device driver functions or (b) a combinationof device driver functions and a DMA controller, depending ona designers decision. The clean separation of information facilitates(1) efficient design space exploration with combinations of differentprocessors, operating systems and protocols, and (2) maintaininga large number of different versions and variants of HW/SWinterfaces by synthesising them on demand. Protocols are specifiedas a grammar, which is fully independent of architecture andimplementation. From this the synthesis tool generates devicedriver code in C and/or synthesizable RTL codein VHDL for DMA controllers. After the initial selection of implementationalternatives the presented methods are fully automated. Its computationalcomplexity is quadratic in terms of the number of states. Withreal-life examples we show that the quality of the generatedcode is close to hand written quality in terms of performance,area and code size.

Grammar based modelling and synthesis of device drivers and bus interfaces

ProGram, a grammar-based communication protocol description language, is used for architectural independent modelling of device drivers and bus interfaces for mixed hardware/software systems. The specification of the protocol is separated from the description of processor bus interfaces and operating system device driver interfaces, which ensures a high efficiency in device driver development and maintenance. A synthesis method for device drivers is presented, together with results on modelling and implementation efficiency for both device drivers and bus interfaces.

Exploration of Tasks Partitioning between Hardware Software and Locality for a Wireless Camera Based Vision Sensor Node

In this paper we have explored different possibilities for partitioning the tasks between hardware, software and locality for the implementation of the vision sensor node, used in wireless vision sensor network. Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate on one dimensional data, wireless vision sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. The research focus within the field of wireless vision sensor networks have been on two different assumptions involving either sending raw data to the central base station without local processing or conducting all processing locally at the sensor node and transmitting only the final results. Our research work focus on determining an optimal point of hardware/software partitioning as well as partitioning between local and central processing, based on minimum energy consumption for vision processing operation. The lifetime of the vision sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of FPGA and micro controller for the implementation of the vision sensor node. Our results show that sending compressed images after pixel based tasks will result in a longer battery life time with reasonable hardware cost for the vision sensor node.

Implementation of Wireless Vision Sensor Node With a Lightweight Bi-Level Video Coding

Wireless vision sensor networks (WVSNs) consist of a number of wireless vision sensor nodes (VSNs) which have limited resources i.e., energy, memory, processing, and wireless bandwidth. The processing and communication energy requirements of individual VSN have been a challenge because of limited energy availability. To meet this challenge, we have proposed and implemented a programmable and energy efficient VSN architecture which has lower energy requirements and has a reduced design complexity. In the proposed system, vision tasks are partitioned between the hardware implemented VSN and a server. The initial data dominated tasks are implemented on the VSN while the control dominated complex tasks are processed on a server. This strategy will reduce both the processing energy consumption and the design complexity. The communication energy consumption is reduced by implementing a lightweight bi-level video coding on the VSN. The energy consumption is measured on real hardware for different applications and proposed VSN is compared against published systems. The results show that, depending on the application, the energy consumption can be reduced by a factor of approximately 1.5 up to 376 as compared to VSN without the bi-level video coding. The proposed VSN offers energy efficient, generic architecture with smaller design complexity on hardware reconfigurable platform and offers easy adaptation for a number of applications as compared to published systems.

Implementation of Wireless Vision Sensor Node for Characterization of Particles in Fluids

Wireless vision sensor networks (WVSNs) have a number of wireless vision sensor nodes (VSNs), often spread over a large geographical area. Each node has an image capturing unit, a battery or alternative energy source, a memory unit, a light source, a wireless link, and a processing unit. The challenges associated with WVSNs include low energy consumption, low bandwidth, limited memory, and processing capabilities. In order to meet these challenges, our paper is focused on the exploration of energy-efficient reconfigurable architectures for VSN. In this paper, the design and research challenges associated with the implementation of VSN on different computational platforms, such as microcontroller, field-programmable gate arrays, and server, are explored. In relation to this, the effect on the energy consumption and the design complexity at the node, when the functionality is moved from one platform to another, are analyzed. Based on the implementation of the VSN on embedded platforms, the lifetime of the VSN is predicted using the measured energy values of the platforms for different implementation strategies. The implementation results show that an architecture, where the compressed images after pixel-based operation are transmitted, realize a WVSN system with low energy consumption. Moreover, the complex postprocessing tasks are moved to a server which has less constraints.

Synthesis of DMA controllers from architecture independent descriptions of HW/SW communication protocols

Starting from an architecture and implementation independent specification of hardware/software communication protocols, we present a protocol synthesis method that generates a mixed hardware and software implementation. For the hardware part, the synthesis method will generate an application specific direct memory access (DMA) controller for each protocol specification. Software parts of the generated implementation are components for initialization, synchronization and communication with the DMA controller. The protocol specification, with the grammar-based language ProGram, is used to model the HW/SW communication protocol. Since this approach is based on a device driver synthesis system for software solutions, which adopts the generated device drivers to a selected processor and kernel, the generated hardware/software solutions can also be adopted to any processor and OS kernel. This lets the designer explore the design space for the communication protocols by trading off between performance and cost.

Asynchronous control of low-power gated-clock finite-state-machines

An efficient approach to reduce power consumption in a synchronous Finite-State Machine (FSM) is to de-compose it, according to a partitioning algorithm, to a number of sub-FSMs that interact through some communication signals. Only one sub-FSM is clocked at a time and low power operation is obtained by only clocking the active sub-FSM. In this paper we introduce a new asynchronous communication control for the interacting sub-FSMs, which reduces the total capacitance switched by the system clock. Experimental results show that this leads to significant power savings when the FSM is partitioned into many sub-FSMs.

Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems

The great variety of pixel dynamics of real-time video-processing systems (RTVPS), ranging from color, grayscale, or binary pixels, means that a careful design and specification of bit widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an integer-nonlinear-program formulation for the optimization of the memory hierarchy of RTVPS. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61% compared to a nonoptimal memory hierarchy