Mauricio Breternitz

Enhanced compression techniques to simplify program decompression and execution

Compressing instruction sequences can reduce the cost of embedded systems by reducing program ROM-size requirements. Compression also facilitates the use of RISC core architectures, like the PowerPC/sup TM/ architecture, in embedded systems. Compression techniques are presented which enable decompression and execution of compressed code to occur without the need of a lookaside table (LAT) or cache lookaside buffer (CLB). These techniques successfully merge code modification and compression into a single software preprocessing step. Decompression and execution of compressed code are made very simple. An application of these techniques to about 120000 instructions of PowerPC firmware code is described.

Motorola PowerPC Migration Tools-emulation and translation

This paper describes the Motorola PowerPC Migration Tools project. The development methodology emphasizes code reuse. Emulation and translation methods are described and characterized. Emulation is applied to ROM-based environments. Translation achieves higher performance by having access to source code.

Design tradeoffs and experience with Motorola PowerPC migration tools

The Motorola PowerPC migration tools enable the conversion of assembly programs from other architectures to PowerPC. This paper describes the design approach and experience with the tool to translate x86 assembly programs to PowerPC. The key problems of handling 16-bit code, the effects of masking 16-bit operations into 32-bit registers and optimization of condition flags are discussed. The efficiency of translation and the effects of architectural constraints on design tradeoffs are analyzed.