Maurizio Bacchetta

Spin-on-glass (SOG) partial etch-back planarization process with 0.4-um gap filling ability

Multilevel interconnection technology requires higher and higher planarization performances, to allow the use of three or more interconnection layers. A high planarization degree is in fact mandatory to avoid process degradation with the increasing number of interconnection layers. The cold planarization scheme, most widely used nowadays, consists in the SOG (spin on glass) deposition, for gap filling, followed by the SOG partial etch-back (PEB) process to remove SOG from the top of metal structures, where VIAs are to be opened. This type of process is, however, limited by SOG gap filling capability. In this paper a new semi-integrated SOG based inter-metal dielectric (IMD) planarization process is shown, capable of filling metal spaces down to 0.4 micrometers , and providing a good long-range planarization degree. The possibility of extending SOG based planarization processes to .35 micrometers generation devices has been successfully demonstrated with the introduction of an oxide tapering process just before SOG coating. The tapering consists of an argon sputter etch, integrated in the same equipment where the first PECVD oxide deposition is performed. Different argon etch conditions were evaluated to obtain the optimal oxide shape. The planarization process was completed with an integrated partial SOG etch-back and PECVD TEOS cap layer deposition process. Results are presented in terms of SOG filling and planarization degree data as a function of gap width and aspect ratio and in terms of process defectivity.

Spin on glass (SOG)-based planarization scheme compatible with a stacked via multilevel metal process

In this work an inter-metal dielectric (IMD) planarization process, developed for multimetal submicron technology devices, is presented. The feasibility to build up to five metal levels with W blanket-etch back stacked plug interconnections is shown, using a new Spin On Glass (SOG) material and a semi-integrated planarization process in which a bake, a SOG Partial Etch Back (PEB), and a TEOS oxide cap layer deposition are done sequentially in the same cluster tool. The presented planarization process allows a very low over-etch for the W etch back step at each plug level and, consequently, a quite good control of the plug recession as required by stacked vias. This new process has effectively extended the life of an existing SOG Partial Etch Back process already established on existing equipment. Planarization process performances have been tested on an advanced triple metal device with stacked W plugs and on a test device with five metal levels with various metal pitches. Process results are presented in terms of defect density, repeatability, and electrical tests on stacked via chain structures.

Inter-metal dielectric planarization process for 0.35 μm multilevel interconnection devices

Abstract A high inter-metal dielectric (IMD) planarization degree is requested in VLSI device manufacturing to avoid process degradation with increasing number of interconnection layers. In this work an IMD planarization process based on the use of spin on glass (SOG) for gap filling followed by SOG partial etch back (PEB) is presented. The main advantage of this process is its capability to provide at the same time long range planarization with the ability to completely fill spaces between metal stripes 0.4 μm wide with an aspect ratio (AR) greater than 2. These results were obtained using a first oxide tapering process and making use of a single thick SOG coating followed by PEB. The planarization performances make the process suitable for the production of three and five metal level interconnection devices of 0.35 μm technology, keeping at the same time the process simple, cheap and highly repeatable.