Maurizio Paolini

Intellectual property re-use in embedded system co-design: an industrial case study

Design of large systems on a chip would be infeasible without the capability to flexibly adapt the system architecture to the application and the re-use of existing Intellectual Property (IP). This in turn requires the use of an appropriate methodology for system specification, architecture selection, IP integration and implementation generation. The goals of this work are: a) verification of the effectiveness of the POLIS HW/SW co-design methodology for the design of embedded systems for telecom applications; b) definition of methodology for integrating system level IP libraries in this HW/SW co-design framework. Methodology evaluations have been carried out through the development of an industrial telecom system design, an ATM node server.

The VHDL based design of the MIDA MPEG1 audio decoder

This paper describes the features and design methodology of MIDA, an MPEGI integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL descriptions, and has been implemented using a cell based approach and a 0.7 /spl mu/m, 2 metal layers CMOS technology. The die area is 95 mm/sup 2/. Synthesis tools have also been used for automatic insertion of test structures and automatic test pattern generation.

Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library

Describes our design experience on fast prototyping with the development of an ASIC for ATM applications from the specification to the final implementation. The main goal of fast and safe prototyping is reached by using the CSELT Intellectual Properties Library of parametric macro-modules. This is a synthesizable library composed of a set of modules, written in RT-level VHDL and implementing functions commonly used in telecom applications. The developed circuit performs the following main functions: UTOPIA/PB interface conversion for both the physical and ATM sides, and ATM cell header processing. The circuit is intended to be used in an ATM switching system and has been designed using a 0.5 /spl mu/m CMOS sea-of-gates library (3.3 V). It has a complexity of 70 kgates and an operational frequency of 33 MHz. The maximum throughput is 155 Mbit/s. It has been developed in approximately three months.

Fast prototyping for telecom components using a synthesizeable VHDL flexible library

A flexible synthesis library for fast and safe prototyping of VLSI circuits for telecom applications is presented. Library modules are described in VHDL so as to be portable in different CAD frameworks and easily usable by IC and system designers. Module flexibility is achieved by using generic parameter programming; mapping can be done on FPGAs, semicustom and cell based CMOS libraries. Modules can reach several thousand gates in size and a target frequency of 40 MHz for a CMOS semicustom design. A VLSI MPEG1 audio decoder developed as a methodology test vehicle is finally detailed.

FPGA design experiences using the CSELT VIP (TM) library

A computer vision camera prototype for real-time applications has been developed. The camera integrates a CMOS image sensor, an FPGA based coprocessing card, and an embedded PC for communication and control tasks. The system is targeted to computer vision tasks where low level processing and feature extraction can be implemented in the PPGA device. The PPGA coprocessing card integrates a medium size FPGA from Xilinx (XC4025E) with two memory banks, an ISA interface, and an image sensor interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system. The camera can be used for hardware/software codesign, research on new computer vision architectures or educational purposes.