Mauro Vasconi

Differential signal scatterometry overlay metrology: an accuracy investigation

The overlay control budget for the 32nm technology node will be 5.7nm according to the ITRS. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further technology development is required to bring it to this level. In this work we present results of a study of an alternative technology for overlay metrology - Differential signal scatterometry overlay (SCOL). Theoretical considerations show that overlay technology based on differential signal scatterometry has inherent advantages, which will allow it to achieve the 32nm technology node requirements and go beyond it. We present results of simulations of the expected accuracy associated with a variety of scatterometry overlay target designs. We also present our first experimental results of scatterometry overlay measurements, comparing this technology with the standard imaging overlay metrology technology. In particular, we present performance results (precision and tool induced shift) and address the issue of accuracy of scatterometry overlay. We show that with the appropriate target design and algorithms scatterometry overlay achieves the accuracy required for future technology nodes.

Diffraction based overlay metrology: accuracy and performance on front end stack

The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty requirements of 0.57 nm for the most challenging use cases of the 32nm technology generation. Theoretical considerations show that overlay technology based on differential signal scatterometry (SCOLTM) has inherent advantages, which will allow it to achieve the 32nm technology generation requirements and go beyond it. In this work we present results of an experimental and theoretical study of SCOL. We present experimental results, comparing this technology with the standard imaging overlay metrology. In particular, we present performance results, such as precision and tool induced shift, for different target designs. The response to a large range of induced misalignment is also shown. SCOL performance on these targets for a real stack is reported. We also show results of simulations of the expected accuracy and performance associated with a variety of scatterometry overlay target designs. The simulations were carried out on several stacks including FEOL and BEOL materials. The inherent limitations and possible improvements of the SCOL technology are discussed. We show that with the appropriate target design and algorithms, scatterometry overlay achieves the accuracy required for future technology generations.

Overlay metrology for double patterning processes

The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOLTM [1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT very challenging. In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique (SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in double patterning processes.

193-nm metrology: facing severe e-beam/resist interaction phenomena

Commercially available photoresists for 193nm litho technology still suffer of undesired phenomena, which could eventually limit the stability of critical layer processing. Also standard CD-SEM inspection has its impact on the overall litho budget, as the interaction between the primary electron beam and the photoresist locally modifies target dimension. The reduction of this effect can be important to preserve geometrical and also electrical characteristics of the chip, as the local variation of the CD is detectable also after target etching and resist removal. In this paper different strategies to reduce its impact onto production wafers are investigated and compared. By applying a combination of these techniques, CD local modification can be lowered up to 75%.

Statistical Aspects of Size Functions for the Description of Random Shapes: Applications to Problems of Lithography in Microelectronics

In applications, objects rarely have exactly the same shape within measurement error; hence the randomness of shapes need to be taken into account. Thanks to the development of information technologies, the last decade has seen a considerable growth of interest in the statistical shape theory and its application to various scientific areas. The solution of the problem of describing a “shape” via functions taking values in a finite dimensional space, without loosing important information, is essential for a mathematical and statistical approach. Recently new geometrical descriptors of shapes, called size functions, have been proposed [4]. These functions are able to capture “globally” the topological and geometrical features of an object, differently from landmarks [2, 6] (which usually are specific points, angles, distances, etc. on the object, chosen by an expert) which are widely used in literature but whose results in a statistical context are strongly dependent on their choice, leading to a sort of subjective quantitative analysis. Size functions depend on the choice of a measuring function and usually only a small number of choices can lead to different statistical results. The theory of size functions has been developed mainly in a deterministic framework. A first attempt to join this theory with randomness is here presented. In particular, we show how to combine size functions with some wellknown statistical techniques in order to obtain good results in random shape recognition and classification [8].

Statistical shape analysis applied to microlithography

In this paper we introduce recent mathematical tools for shape description called size functions. Some features of these descriptors such as robustness with respect to noise are pointed out. A first attempt to join the theory of size functions with randomness and to develop the related statistical analysis is then presented. The resulting procedure is applied to some specific problems which arise in microlithography of electronic devices.

Evaluation of Hitachi CAD to CD-SEM metrology package for OPC model tuning and product devices OPC verification

Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193nm resists, much more sensitive to SEM e-beam exposure if compared to 248nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues. In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy. The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

In-chip optical CD measurements for non-volatile memory devices

A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

Near and sub-half-micrometer geometry SEM metrology requirements for good process control

Over the past ten years lpw kV Electron Microscopy has been the technique of choice for inprocess, critical layer metrology, for leading-edge design-rule devices. However, conventional low kY Secondary Electron microscopy is reaching its limits in its ability to measure near and sub-half micron features at all levels due to charging issues and interpretation of resist profile. A re-evaluation of the strategy for determining CD measurement site becomes increasingly important as site to site differences are more significant at these smaller dimensions. Otherwise an apparently well controlled process measured in a typical site (e.g. array of a memoiy cell) could be failing due to shorts in critical sites. These critical sites tend to challenge the limits of conventional SEM metrology more. A new generation of SEMs offering a variety of techniques to overcome these limitations has recently arrived on the market, these improve visibility and reduce the effects of charging, allowing a more accurate and representative control ofa lithographic process to be made.