Md. Liakot Ali

Development of mobile phone based surveillance system

In todays world, ensuring security for important locations is a burning issue. Different surveillance methodologies such as alarm system, CCTV, PC based video system are used to ensure this security. But using all these systems, it is not possible for a person to monitor the security of his or her desired location when they are outside. Now-a-days anybody can communicate with anyone at anytime around the globe with the help of mobile phone technology. By keeping the technological facility of mobile phone in mind, a mobile phone based surveillance system has been described in this paper. This paper will give a solution for the security of corporate houses as well as corporate personnel. In this system there are server and client end. Server will store images being captured by the webcam of an important location. Then based on clients request sending from their mobile phone to the server, clients will be able to view the images from their mobile phone that is stored in the server. Clients are also able to move the webcam by sending control instruction from their mobile phone to view the images of their desired position. The developed system has been tested first using the GUI (emulator) designed by NetBeans IDE. It has also been tested using different mobile phones to see the images in real time and it provides the true sense of real mobility and security by accessing the desired location from the mobile phone anytime anywhere whenever wishes. This surveillance system can also be implemented for other handheld devices like PDA.

RFID based e-monitoring system for municipal solid waste management

With the increase of population of a country, proper management of cumulative of Municipal Solid Waste (MSW) becomes more acute for maintaining green environment. In conventional approach a number of trucks collect the MSW and then transport and transfer these MSW in a pre-specified location, but all the above jobs are not properly monitored. It is very important to monitor the trucks and record the information related to the collecting time and area from a central location to ensure the job well done. This project exploits the tremendous power of RFID technology and presents the development of an electronic monitoring (e-monitoring) system to overcome the above problem in the conventional approach. The proposed e-monitoring system is an embedded system that consists of RFID technology interfaced with PIC micro-controller and a web based computerized software. It has been tested in the laboratory environment as well as in the field environment. The test results show that the system functions properly and is working real time. Municipal authority can monitor the SW collecting status through the system and can generate different reports to improve the performance of their service. The prototype developed in this project can be further improved and used for commercial purpose.

A Novel Byte-Substitution Architecture for the AES Cryptosystem

The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture is discussed for both CMOS and FPGA platforms, and the pipelined architecture of the proposed S-box is presented for further time savings and higher throughput along with higher hardware resources utilization. A performance analysis and comparison of the proposed architecture is also conducted with those achieved by the existing techniques. The results of the comparison verify the outperformance of the proposed architecture in terms of power, delay and size.

Development of a novel prepaid gas metering system

Energy saving by mitigating the waste of energy and save the world from global warming is a very common concern of this day. This paper presents the design and implementation of a prototype novel contactless smartcard based prepaid metering system for domestic purpose that technologically forces the customers to stop the misuses of natural gas. The proposed metering system addresses all the drawbacks of our previously developed and deployed 4500 meters in a pilot site at Dhaka. The functionality of the meter has been tested in the laboratory and demonstrated to the utility company (KGDCL). The proposed meter is more efficient in terms of power consumption, more secured and more user friendly in terms of vending the smart card and top-up the meter than those of its earlier version.

Development of a translation model from HTML to WML using component based information extraction technique

Now-a-days mobile is part of our daily life. So mobile browsing is becoming popular issue day by day. Today most web pages are written in HTML. Mobile Browsers are optimized for displaying web content. It has low-memory capacity and low-bandwidth. So, mobile browser cannot render all html documents in its limited area. Specific information of particular web page needs to visualize for mobile users. So the effective conversion from HTML to WML becomes a key issue for reducing tedious work. In this technique, not only convert static content, but also some sort of dynamic content will be converted and it improved the conversion effectively in speed and accurate rate, whilst presented the useful information conveniently to the users.

Design of low power decimal logarithmic converter

The paper presents the design of an efficient low power decimal logarithmic converter. The technique is based on shift operation along with a precision unit which is used to prevent unnecessary scan of full memory table. Precision level is user programmable. It does not require multiplication or division circuitry which in turn makes it low power. The synthesized results show that the proposed technique costs (6002 logic element) and consuming power (only 47.37mW) which is lowest than other related algorithm. The design has been implemented in FPGA platform and proposed design outperforms all the existing design of the said topic.

Design of a Hummingbird Crypto Core implementing BIST technique

In recent years, lightweight cryptography which focuses on designing new cryptographic primitives with small hardware footprint and with low average and peak power consumption, has received a lot of attention. Hummingbird, an ultra-lightweight cryptographic algorithm has been developed both with lightweight software and lightweight hardware implementations keeping resource-constrained devices in mind. In this paper, we describe FPGA implementation with both software simulation as well as HW implementation of Hummingbird algorithm on Altera Platform. Moreover, testability of a complex chip is of prime concern now a days. Built-In-Self-Test (BIST) is a widely accepted approach for this purpose. In this paper design of a Hummingbird Crypto Core implementing BIST technique is proposed and both software and hardware implementation is performed. Here LFSR is used as pseudorandom test pattern generator and Signature Analysis is used as a Data Compression Technique. The proposed Crypto Core is simulated in Quartus II simulation software for the Altera Cyclone II family device as well as hardware implementation done in Altera DE2 board and performance is analyzed and compared with the other research works on Hummingbird implementation.

Design of a high speed OFDM transmitter and receiver

System-on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platforms such as FPGA, CPLD, and PLD are now being used for designing and implementing SoC due to their low cost, high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver have been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX and LTE etc. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio broadcasting, Asynchronous Digital Subscriber Line (ADSL) and High bit-rate Digital Subscriber Line (HDSL) systems. In OFDM, two algorithms digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8-point IFFT/FFT Decimation-In-Frequency (DIF) with radix-2 algorithm has been analyzed and incorporated in the design. The design has been simulated on the FPGA platform with Alteras Quartus II simulator. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.

Design of a double AES processor

Advanced Encryption Standard (AES) is now widely used in different kinds of applications in software and hardware implementations. This paper presents the design and simulation of a double AES processor to explore the performance matrixes such as logic gates, speed and cost for the next generation IT security. Design of both Encryption and Decryption modules are carried out and simulated in an iterative design approach to minimize the hardware consumption. Here the operation like substitution bytes, mix column are simplified to reduce complexity and to produce a simple design which would deliver a high throughput and minimum latency.

Development of an FPGA based low power message displaying system using scanning technique

Power efficient solution is essential for the portable electronic system. This paper presents an FPFA based embedded system for low power message display. Scanning technique is used to minimize the power. Experiment is conducted on 30 seven segments where an FPGA based intelligent controller scans all the display elements continuously at a certain speed to ensure only one display unit is on and other are off at a given time but human eye cannot detect it. Test result shows the significant reduction of power consumption over static display system.