Meng Chuan Lee

Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices

Technology scaling challenges for flash memory beyond 30 nm exacerbated as device fundamental limits are fast approaching. Nitride-based charge trap flash (CTF) is one of the most viable alternatives to eclipse floating gate flash in the market by leveraging the existing materials as compared with other exploratory nonvolatile memory devices. However, postcycled threshold voltage instability in the form of charge loss (CL) mechanisms remains as critical reliability challenges to further improve long-term data retention performance. This paper focuses on long-term data retention reliability issues with an emphasis on major CL mechanisms of nitride-based CTF memory. It encompasses comprehensive reviews and discussions on major CL mechanisms due to intrinsic and extrinsic causes. This paper would serve as a good reference for the future development of nitride-based CTF memory.

Technical solutions to mitigate reliability challenges due to technology scaling of charge storage NVM

Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order tomeet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run intomany critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.

Anomalous threshold voltage variability of nitride based charge storage nonvolatile memory devices

Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM) devices. In this study, effect of technology scaling to anomalous threshold voltage (Vt) variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cells (Vt) variability of each subsequent bake increases within stable (Vt) distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous (Vt) variability was derived through Arrhenius plots. Apparent activation energy (Eaa) of this anomalous (Vt) variability is 0.67 eV at sub-40nm devices which is a reduction of approximately 2 times from 110nm devices. Technology scaling clearly aggravates this anomalous (Vt) variability, and this poses reliability challenges to applications that demand strict (Vt) control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous (Vt) variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Abstract Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.

Investigation on the Impact of Program/Erase Cycling Frequency on Data Retention of Nanoscale Charge Trap Nonvolatile Memory

This letter presents a detailed study to investigate the impact of program/erase (P/E) cycling frequency on threshold voltage (Vt) instability of nanoscale nitride-based charge trap nonvolatile memory (NB-CTNVM) devices. Post-P/E cycled Vt instability was found to exacerbate with higher P/E cycling frequency, which resulted in lower activation energy (Ea). The Ea obtained is 30% higher than those of floating gate NVM. In view of future demand for faster write speed of NVM devices, these findings indeed have critical impact on the selection of the acceleration factor and Ea applied to assess accurately the reliability performance of nanoscale CTNVM.