Meng-Ju Chiang

Design of Synthetic Quasi-TEM Transmission Line for CMOS Compact Integrated Circuit

This paper presents the design guidelines of the synthetic quasi-TEM transmission line (TL) based on standard 0.18 mum one-poly six-metal complementary metal-oxide-semiconductor (CMOS) technology. The synthetic quasi-TEM TL, also called the complementary-conducting-strip transmission line (CCS TL), is composed of five structural parameters to synthesize its guiding characteristics. Twenty-four designs of CCS TL are reported, with the following unique attributes. First, a characteristic impedance range of 8.62-104.0 Omega is yielded. Second, the maximum value of the slow-wave factor is 4.79, representing an increase of 139.5% over the theoretical limit of the quasi-TEM TL. Third, the ratio of the area of the CCS TL to its corresponding quality factor ( factor) can help to estimate the cost of the loss for the circuit miniaturizations. Additionally, the important CMOS manufacturing of metal density is for the first time involved in the reported TL designs. By following the proposed design methodologies, a practical design example of a -band CMOS rat-race hybrid is reported and experimentally examined in detail to reveal the feasibility of the proposed design guidelines to synthesize the CMOS CCS TL. The chip size without contact pads is 420.0 mum 540.0 mum. The measured loss and isolation of the hybrid at 36.3 GHz are 3.84 and 58.0 dB, respectively.

Artificial-Synthesized Edge-Coupled Transmission Lines for Compact CMOS Directional Coupler Designs

This paper presents artificial-synthesized edge- coupled transmission lines (TLs) based on complementary metal- oxide semiconductor (CMOS) technology. The artificial coupled- line (CL), the so-called the complementary-conducting-strip coupled line (CCS CL), consists of the unit cell and is meandered in the 2-D plane. The unit cell, whose dimensions are much smaller than the guiding wavelength at the operating frequency, provides five structural parameters for CL syntheses. The synthesized CLs, which are fully characterized by using theoretical and experimental procedures, reveal the following unique guiding properties. First, the coupling coefficient (K) can be 7.7% higher than that of the meandered conventional edged-coupled TLs. Second, the even- and odd-mode propagation constants can be synthesized as identical at the same time. Two backward-wave directional couplers for achieving the tight coupling and high directivity are designed by incorporating artificial CCS CL. Two prototypes are fabricated by the standard 0.18-¿m CMOS technology, occupying the chip areas of 120.0 ¿m × 240.0 ¿m. The measured results show that the isolation is higher than 25.0 dB from 10.0 to 40.0 GHz with a coupling of 14.4 dB. On the tight coupler design, the through and coupling are 4.65 ± 0.15 dB from 30.0 to 40.0 GHz with an amplitude imbalance of less than 0.3 dB.

A Ka-Band CMOS Wilkinson Power Divider Using Synthetic Quasi-TEM Transmission Lines

This work presents a Ka-band two-way 3 dB Wilkinson power divider using synthetic quasi-transverse electromagnetic (TEM) transmission lines (TLs). The synthetic quasi-TEM TL, also called complementary-conducting-strip TL (CCS TL), is theoretically analyzed. The equivalent TL model, whose production is based on the extracted results, is applied to the power divider design. The prototype is fabricated by the standard 0.18 mum 1P6M CMOS technology, showing the circuit size of 210.0 mumtimes390.0 mum without contact pads. The measurement results, which match the 50 Omega system, reveal perfect agreements with those of the simulations. The comparison reveals the following characteristics. The divider exhibits an equal power-split with the insertion losses (S21 and S31) of 3.65 dB. The return losses (S11, S22 and S33) of the prototype are higher than 10.0 dB from 30.0 to 40.0 GHz.

A compact CMOS Marchand balun incorporating meandered multilayer edge-coupled transmission lines

This work presents a compact CMOS Marchand balun design, which consists of the meandered two-conductor edge-coupled complementary-conducting-strip coupled-line (CCS CL). The CCS CL, which is fully compatible with the standard CMOS process, provides various structural parameters to synthesize the desired coupling coefficient for Marchand balun realization. The prototype, which is fabricated by the standard 0.18-µm 1P6M CMOS technology, reveals circuit size of 240.0 µm × 240.0 µm (without contact pads). The measured results, which are collected based on 50-Ω system, demonstrate excellent agreements with those of the simulations. The input return loss is less than −15.0 dB from 21.6 GHz to 33.1 GHz. The measured insertion losses between input and two output ports (S21 and S31) are 5.90 dB and 4.38 dB at 23.6 GHz, respectively. The phase difference between two output ports is 180° ± 10° from 15.5 GHz to 40.0 GHz.

A 3.3 mW K-Band 0.18-

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P1 dB and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.

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Design of CMOS 3-dB directional coupler by incorporating the edge-coupled meandered synthetic quasi-TEM transmission lines (TLs) is presented. The proposed synthetic TL, so-called the complementary-conducting strip coupled-line (CCS CL) consists of the unit cell, which has more design parameters than that of the conventional thin-film coupled-line (TF CL). The extensive theoretical analyses shows the proposed meandered CCS CL can break the process limitations on straight TC CL, achieving the coupling coefficient (k-value) with 10.8% improvement. The prototype of the 3-dB directional coupler is designed based on the proposed CCS CL and fabricated in an area of 120.0 × 240.0 μm (without contact pads) based on the standard 0.18-μm 1P6M CMOS technology. The experiments show the prototype can cover a bandwidth from 14.2 GHz to 36.9 GHz with a coupling of 4.5 dB. The literature survey shows that the presented design achieves the tight coupling with the highest efficiency on the circuit miniaturization.

m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

Design of a CMOS spiral inductor of significantly reduced coupling to the adjacent inductor is presented. The synthetic quasi-TEM transmission line (TL), or the so-called complementary-conducting-strip transmission line (CCS TL), is applied to realize the proposed inductor and simultaneously shield electromagnetic coupling from the adjacent inductor by the existing meshed ground plane of the CCS TL. Several coupled inductors at edge-to-edge spacing of 90 mum, 170 mum, and 250 mum were fabricated by the 1P6M (one poly-layer and six metal layers) 0.18 mum CMOS process, demonstrating excellent broadband shielding characteristics of approximately 30-to-40 dB improvement below 5 GHz and 15 dB improvement at 20 GHz when compared with the same spirals integrated on the CMOS substrate directly without shields

A CMOS 3-dB directional coupler using edge-coupled meandered synthetic transmission lines

This paper presents a compact Ka-band monolithic branch-line coupler using synthetic transmission line (TL). The prototype, which is fabricated by the standard 0.18-µm 1P6M CMOS technology, shows the circuit size of 300.0 µm × 360.0 µm (1.48 × 10⁻³ λ²<inf>0</inf> ) without contact pads, achieving 95.1% size reduction. The measured results show the excellent agreements with those of the simulations. The measured insertion loss is 4.9 dB and the return loss is kept higher than 10.0 dB from 28.8 GHz to 39.1 GHz. The isolation of the coupler is higher than 15.0 dB and has a maximum value of 23.0 dB at 37.0 GHz. The measured frequency range of phase difference (90° ± 10°) between two output ports is 4.5 GHz from 31.1 GHz to 35.6 GHz.

Design of CMOS Spiral Inductors for Effective Broadband Shielding

This paper presents a CMOS miniaturized phase-invertible variable attenuator (PIVA) at K-band. The PIVA only consists of one 3-dB transmission line (TL) based directional coupler, two NMOS transistors, and simple matching network. The technique of complex impedance matching is proposed to improve the precision of the phase reversal, and reduce the phase shifting of the PIVA. Furthermore, the 3-dB coupler, which is realized by the edge-coupled synthetic transmission lines, so-called the complementary-conducting strip coupled lines (CCS CLs), is applied to PIVA design for the circuit miniaturization. The presented attenuator design is analyzed and fabricated by using standard 0.18 µm 1P6M CMOS technology. The prototype, which has only a chip size of 242 µm × 246 µm excluding the contacting pads, are experimentally characterized through the on-wafer measurements. The measured phase reversal is 181.4 degree, nearly approaching to the ideal state. From 20 to 28 GHz, the measured attenuation dynamic range is more than 20 dB with a phase shifting less than 8.8 degree. The input and output return losses are lower than −10.2 and −11 dB, respectively.

Design of compact Ka-band monolithic branch-line coupler on silicon substrate

Multilayer synthetic quasi-TEM transmission lines (TLs) are applied to the CMOS hybrids miniaturization. Two meandered synthetic quasi-TEM TLs are integrated in the form of CMOS multilayer structure and shielded by the mesh ground plane. Theoretical analyses are performed to extract the guiding properties of the multilayer synthetic quasi-TEM TLs. The extracted results are applied to the CMOS hybrid designs. The prototypes of Ka-band power divider and 180-degree hybrid (rat-race hybrid) are implemented by using the standard 0.18-mum 1P6M CMOS technology, achieving the circuit sizes of 180.0 mum times 180.0 mum and 210.0 mum times 480.0 mum, respectively. The experiments show intrinsic loss of power divider is less than 5.26 dB over a bandwidth of 10-GHz when the input return loss is kept higher than 10.0 dB. In the rat-race design, the measured insertion loss is 4.98 dB and the isolation is higher than 17.0 dB.