Mengyuan Hua

Characterization of Leakage and Reliability of SiN x Gate Dielectric by Low-Pressure Chemical Vapor Deposition for GaN-based MIS-HEMTs

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole-Frenkel emission at low electric field and Fowler-Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated.

O3-sourced atomic layer deposition of high quality Al2O3 gate dielectric for normally-off GaN metal-insulator-semiconductor high-electron-mobility transistors

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al–O–H and Al–Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 × 1012 cm−2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm2.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Low On-Resistance Normally-Off GaN Double-Channel Metal–Oxide–Semiconductor High-Electron-Mobility Transistor

A low on-resistance normally-off GaN double-channel metal-oxide-semiconductor high-electronmobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with Vth of +0.5 V at IDS = 10 μA/mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/(V·s). The on-resistance is as small as 6.9 Q·mm for a DC-MOS-HEMT with LG/LGS/LGD = 1.5/2/15 μm, and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. Index Terms-Double-channel MOS-HEMT (DC-MOSHEMT), field-effect mobility, gate recess, normally-off.

Integration of LPCVD-SiN x gate dielectric with recessed-gate E-mode GaN MIS-FETs: Toward high performance, high stability and long TDDB lifetime

By employing an interface protection technique to overcome the degradation of etched GaN surface in high-temperature process, highly reliable LPCVD-SiN<inf>x</inf> gate dielectric was successfully integrated with recessed-gate structure to achieve high-performance enhancement-mode (V<inf>th</inf> ∼ +2.37 V @ I<inf>d</inf> = 100 μA/mm) GaN MIS-FETs with high stability and high reliability. The LPCVD-SiN<inf>x</inf>/GaN MIS-FET delivers remarkable advantages in high Vth thermal stability, long time-dependent gate dielectric breakdown (TDDB) lifetime and low bias temperature instability (BTI).

Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess

An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.

Compatibility of AlN/SiN x Passivation With LPCVD-SiN x Gate Dielectric in GaN-Based MIS-HEMT

In this letter, we demonstrate an integrated process that illustrates the compatibility of AlN/SiNx passivation with high-performance (i.e. low leakage and high breakdown) low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric for GaN-based MIS-HEMT. It is shown that the AlN/SiNx passivation structure maintains its superior capability of suppressing the current collapse after enduring high temperature of 780 °C during the LPCVD-SiNx deposition. The AlN/SiNx passivation is shown to be significantly better than the LPCVD-SiNx passivation by delivering small dynamic RON degradation, especially under high drain bias switching with VDS > 100 V.

650-V GaN-based MIS-HEMTs using LPCVD-SiNx as passivation and gate dielectric

In this work, silicon nitride (SiNx) film deposited at 780 °C by low pressure chemical vapor deposition (LPCVD) was employed as the passivation layer and gate dielectric for GaN-based MIS-HEMTs. The LPCVD-SiNx/AlGaN/GaN MIS-HEMTs exhibit suppressed current collapse, small gate leakage current at both reverse and forward gate bias, high forward gate breakdown voltage and high time dependent gate dielectric reliability.

Enhanced Dielectric Deposition on Single-Layer MoS2 with Low Damage Using Remote N2 Plasma Treatment

Using remote N2 plasma treatment to promote dielectric deposition on the dangling-bond free MoS2 is explored for the first time. The N2 plasma induced damages are systematically studied by the defect-sensitive acoustic-phonon Raman of single-layer MoS2, with samples undergoing O2 plasma treatment as a comparison. O2 plasma treatment causes defects in MoS2 mainly by oxidizing MoS2 along the already defective sites (most likely the flake edges), which results in the layer oxidation of MoS2. In contrast, N2 plasma causes defects in MoS2 mainly by straining and mechanically distorting the MoS2 layers first. Owing to the relatively strong MoS2-substrate interaction and chemical inertness of MoS2 in N2 plasma, single-layer MoS2 shows great stability in N2 plasma and only stable point defects are introduced after long-duration N2 plasma exposure. Considering the enormous vulnerability of single-layer MoS2 in O2 plasma and the excellent stability of single-layer MoS2 in N2 plasma, the remote N2 plasma treatment shows great advantage as surface functionalization to promote dielectric deposition on single-layer MoS2.

Gate stack engineering for GaN lateral power transistors

Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables optimal trade-off between performance and stability; (3) bulk quality and reliability enhancement of the gate dielectric. These gate-stack techniques in terms of new process development and device structure design are valuable to realize highly reliable and competitive GaN power devices.