Meysam Asadi

Optimal Detector for Multilevel NAND Flash Memory Channels with Intercell Interference

In this paper we derive the optimal detector for multilevel cell (MLC) flash memory channels with intercell interference (ICI). We start with the MLC channel model proposed by Dong et al. and just slightly alter the model to guarantee mathematical tractability of the optimal detectors (maximum likelihood and maximum a-posteriori sequence and symbol detectors). The optimal detector is obtained by computing branch metrics using Fourier transforms of analytically computable characteristic functions (corresponding to likelihood functions). We derive the detectors for both simple one-dimensional (1D) channel models and more realistic page-orientated two-dimensional (2D) channel models. Simulation results show that the hard-output bit error rate (BER) performance matches some previously known detectors, but that the soft-output detector outperforms previously known detectors by 0.35 dB.

All-bit-line MLC flash memories: Optimal detection strategies

We are concerned with the optimal detector design for the all-bit-line MLC flash memory. We provide a channel model of the MLC flash memory, where the channel parameters are mathematically tractable. Then we present an optimal maximum a-posteriori sequence detector. The optimal detector can be executed over a trellis whose branch metrics can be computed by using Fourier transforms of analytically computable characteristic functions (corresponding to likelihood functions). The soft-output detectors for both simple one-dimensional channel models and more realistic page-orientated two-dimensional channel models are derived. Simulation results show not only that the soft-output detector has the same hard-output bit-error-rate performance as some previously known detectors did, but that the soft-output detector outperforms previously known detectors by a gain of 0.23 dB.

Write process modeling in MLC flash memories using renewal theory

In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of “renewal processes”. Then, we approximate the maximum number of steps in iterative programming, and obtain the voltage distribution in flash due to iterative programming. Moreover, the obtained results help us to accurately analyze the effect of inter-cell interference (ICI) in this type of memory. Finally, we obtain a more precise voltage distribution for the symbol states in flash memory. Simulation results show the effect of varying the step size in the iterative programming and the effect of ICI on the information rate.

Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs

In the write process of multilevel per cell (MLC) flash memories, an iterative approach is used to mitigate the monotonicity problem. The monotonicity in programming is considered to be the major restriction in MLC flash. To solve this issue, an iterative approach called incremental step pulse programming (ISPP) is used to concurrently program lots of cells in small steps. In this paper, we are mostly concerned with deriving a mathematical model for iterative programming using the framework of renewal theory. We obtain a closed-form approximation for the probability distribution of the number of steps required in the ISPP process. We also bound the maximal error between the true distribution and our approximation. Moreover, the results obtained help to accurately analyze the effect of inter-cell interference in this type of memory. Finally, we devise an adaptive step size approach for write process to strike a balance between latency and lifetime under fixed bit error rate constraints or information rate constraints.