Michael A. Epstein

Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts

There are many applications for true, unpredictable random numbers. For example the strength of numerous cryptographic operations is often dependent on a source of truly random numbers. Sources of random information are available in nature but are often hard to access in integrated circuits. In some specialized applications, analog noise sources are used in digital circuits at great cost in silicon area and power consumption. These analog circuits are often influenced by periodic signal sources that are in close proximity to the random number generator. We present a random number generator comprised entirely of digital circuits, which utilizes electronic noise. Unlike earlier work [11], only standard digital gates without regard to precise layout were used.

The design of a RISC based multiprocessor chip

The architecture of an RISC (reduced instruction set computer) based on multiprocessor chip designed in the Briarcliff Multiprocessor Project is described. The processors operate in an MIMD (multiple instruction, multiple data) fashion, executing parallel instruction streams generated by a parallelizing compiler for the exploitation of fine-grained parallelism. Low-cost synchronization mechanisms are supported in hardware. The resulting system is tolerant of unpredictable delays in the progress of individual streams. Instruction level parallelism is exploited through the use of register channels and a mechanism for the collective branching of processors. For efficient synchronization during parallel execution of loops, fuzzy barriers are provided. On-chip memory is organized into multiple banks in order to provide sufficient bandwidth for the processors. The RISC processors are based upon the Sun SPARC architecture.<<ETX>>

Achieving low cost synchronization in a multiprocessor system

A barrier are a commonly used mechanism for synchronizing processors executing in parallel. A software implementation of the barrier mechanism using shared variables has two major drawbacks. First, the synchronization overhead is high and second, when a processor reaches the barrier it must idle until all processors reach the barrier. In this paper, the fuzzy barrier, a mechanism that avoids the above drawbacks, is presented. The first problem is avoided by implementing the mechanism in hardware. The second problem is solved by using software techniques to find useful instructions that can be executed by a processor while it awaits synchronization. The hardware implementation eliminates busy waiting at barriers, provides a mask that allows disjoint subsets of processors to synchronize simultaneously, and provides multiple barriers by associating a tag with a barrier. Compiler techniques are presented for constructing barrier regions which consist of instructions that a processor can execute while it is waiting for other processors to reach the barrier. The larger the barrier region, the more likely it is that none of the processors will have to stall. Initial observations show that barrier regions can be large and the use of program transformations can significantly increase their size.

Security for the digital information age of medicine: Issues, applications, and implementation

Privacy and integrity of medical records is expected by patients. This privacy and integrity is often mandated by regulations. Traditionally, the security of medical records has been based on physical lock and key. As the storage of patient record information shifts from paper to digital, new security concerns arise. Digital cryptographic methods provide solutions to many of these new concerns. In this paper we overview new security concerns, new legislation mandating secure medical records and solutions providing security.

Achieving Low Cost Synchronization in a Multiprocessor System

A barrier are a commonly used mechanism for synchronizing processors executing in parallel. A software implementation of the barrier mechanism using shared variables has two major drawbacks. First, the synchronization overhead is high and second, when a processor reaches the barrier it must idle until all processors reach the barrier. In this paper, the fuzzy barrier, a mechanism that avoids the above drawbacks, is presented. The first problem is avoided by implementing the mechanism in hardware. The second problem is solved by using software techniques to find useful instructions that can be executed by a processor while it awaits synchronization. The hardware implementation eliminates busy waiting at barriers, provides a mask that allows disjoint subsets of processors to synchronize simultaneously, and provides multiple barriers by associating a tag with a barrier. Compiler techniques are presented for constructing barrier regions which consist of instructions that a processor can execute while it is waiting for other processors to reach the barrier. The larger the barrier region, the more likely it is that none of the processors will have to stall. Initial observations show that barrier regions can be large and the use of program transformations can significantly increase their size.