Michael A. Soderstrand

CSD multipliers for FPGA DSP applications

The canonic sign digit (CSD) number system is both a technique for representing fixed-point numbers and an algorithm for multiplying one fixed-point number by another. Through the addition of look-up-table (LUT) based control logic, the simple CSD scaler (ie: fixed-coefficient multiplier) can be converted to a hardware-efficient full four-quadrant multiplier with applications in adaptive filters, digital up-converters and down-converters, Two novel circuits are designed to take advantage of the Xilinx FPGA architecture to provide simple, yet hardware-efficient multipliers. The multipliers are designed for application in adaptive digital filters, Fourier transforms, and other DSP applications that require an efficient four-quadrant multiplier.

Reducing hardware requirement in FIR filter design

A hardware optimization scheme based upon minimum-adder CSD multiplier blocks is combined with a technique for trading adders for delays to reduce hardware requirements for fixed-coefficient FIR filters well below that achieved with either technique alone. The technique starts with determining the minimum order filter necessary to meet the filter specifications assuming infinite precision filter coefficients. Then the coefficients are truncated to B bits (which may be specified by the designer) and the order of the filter is increased, if necessary, to meet the filter specifications. From this baseline filter, an exhaustive search is carried out by increasing the filter order (adding delays) and decreasing the bits (decreasing adders) to search for the minimum hardware. At each search point, the minimum-adder CSD multiplier block approach is used to assure the optimum hardware realization. The result is the implementation in FPGAs or VLSI of FIR filters with less real estate and/or with less power consumption.

Comparison of various numerically controlled oscillators

A numerically-controlled oscillator (NCO) based upon the COordinate Rotational DIgital Computer (CORDIC) algorithm offers less hardware than the direct form digital NCO at the expense of a second clock that may be as much as N/2 times the nyquist frequency of the system, where N is the number of bits in the NCO output. The CORDIC NCO also uses less hardware than the popular look-up table (LUT) based NCO. Both the LUT NCO and the CORDIC NCO require the additional clock, but the CORDIC clock is easier to synchronize than the LUT NCO clock.

Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation

Savings ranging from 36% to 53% in FPGA resources are achieved through a filter design program that simultaneously applies optimum scaling, careful selection of filter order and use of fixed-coefficient multipliers designed with CSD and/or DM techniques. The output of the program is a VHDL description of the optimized hardware that is suitable as input to the Synplify Pro computer program that generates highly optimized FPGA circuits for Xilinx and other FPGAs.

Improved numerically-controlled digital sinusoidal oscillator

The design of a digital sinusoidal oscillator with finite word length having excellent capability to reduce DC drift, frequency and amplitude drifts is proposed. The design utilizes the fundamental properties of a simple second order difference equation. The key element of this NCO is a ROM look-up-table (LUT) that translates the control input into a value of beta (the cosine of the desired frequency angle theta) that guarantees stability of the oscillator. The disadvantage is that the frequency of oscillation may be slightly different from that specified by the NCO input. But the result is an oscillator that has zero drift in amplitude, DC value or frequency. The proposed oscillator utilizes an LUT, a single multiplier, two input adders and two delays. Simulations confirm the no DC drift, no amplitude distortion and no frequency drift occur for long-term oscillation.

Maximizing channel capacity in FSK modulation systems

In binary FSK modulation schemes the transition between the two frequencies f/sub 0/ representing a ZERO and f/sub 1/ representing a ONE is governed by the shape of the input pulse as it makes its transition from a ZERO to a ONE. Through the use of an optimum filter, it is possible to shape the pulse in such a way as to maximize the speed of transition from f/sub 0/ to f/sub 1/ while maintaining signal energy outside of the channel to specified small levels. In this paper, we describe a procedure for finding optimum filters for several important types of FSK modulation.

High-range switched-capacitor tracking filter

A high-range switched-capacitor (SC) filter capable of tracking sinusoid signals without the need of a reference is presented. The filter tracks sinusoids by adapting the sampling clock of the switched-capacitors. An important feature of this filter is its ability to track sinusoid signals in cases where the frequency of the signal and the center frequency of the filter are off by several octaves. This is particularly useful in applications were the range of frequencies of the signal is very wide.

Simple adaptive heterodyne filter

The tuning of the band pass filter in the simple heterodyne filter structure can be done over a range of 90-degrees by changing the heterodyne frequency. However in this, the heterodyne frequency is constant and can be made adaptive by introducing a Numerical Controlled Oscillator. The proposed design structure uses the Numerical Controlled Oscillator output that can be used as the heterodyne frequency so as to tune the band pass filter effectively.

Hardware efficient BPSK and QPSK detector

A very simple LMS-based adaptive notch filter implemented in FPGAs can be used for carrier recovery of a QPSK signal and for direct detection of a BPSK signal. The key aspect of our paper lies in the alternative approach in the realization of carrier frequency detection or synchronization circuit. The carrier frequency after detection is used in the conventional QPSK detector. Also the demodulator has a simple hardware realization that does not require a reference signal.

CORDIC implementation of digital heterodyne filter in VLSI

CORDIC (Coordinate Rotation Digital Computer) is an iterative digital algorithm, which allows rapid rotation of coordinates in the digital plane. The CORDIC can be used for the calculation of trigonometric functions. This iterative method of performing the transformations uses only shifts and adds. Significant savings in hardware can be achieved through the implementation of the heterodyne circuits of modulators, demodulators and filters using the CORDIC algorithm. In particular, significant hardware savings can be achieved in the implementation of a digital heterodyne filter in VLSI using the CORDIC algorithm.