Michael David May

Message routing scheme

SYNCHRONISATION IN A MULTITHREADED PROCESSOR

PROCESSOR COMMUNICATION TOKENS

Processor instruction set

Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor

Data transfer between thread register sets

Processor instruction set for controlling threads to respond to events

Scheduling thread upon ready signal set when port transfers data on trigger time activation

Message routing scheme for an array having a switch with address comparing component and message routing component

Processor architecture for use in scheduling threads in response to communication activity