Michael E. Deisher

Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU

Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an important aspect for emerging applications. Our analysis of a set of important throughput computing kernels shows that there is an ample amount of parallelism in these kernels which makes them suitable for todays multi-core CPUs and GPUs. In the past few years there have been many studies claiming GPUs deliver substantial speedups (between 10X and 1000X) over multi-core CPUs on these kernels. To understand where such large performance difference comes from, we perform a rigorous performance analysis and find that after applying optimizations appropriate for both CPUs and GPUs the performance gap between an Nvidia GTX280 processor and the Intel Core i7-960 processor narrows to only 2.5x on average. In this paper, we discuss optimization techniques for both CPU and GPU, analyze what architecture features contributed to performance differences between the two architectures, and recommend a set of architectural features which provide significant improvement in architectural efficiency for throughput kernels.

Activity recognition and monitoring using multiple sensors on different body positions

The design of an activity recognition and monitoring system based on the eWatch, multi-sensor platform worn on different body positions, is presented in this paper. The system identifies the users activity in realtime using multiple sensors and records the classification results during a day. We compare multiple time domain feature sets and sampling rates, and analyze the tradeoff between recognition accuracy and computational complexity. The classification accuracy on different body positions used for wearing electronic devices was evaluated

Trading off prediction accuracy and power consumption for context-aware wearable computing

Context-aware mobile computing requires wearable sensors to acquire information about the user. Continuous sensing rapidly depletes the -wearable systems energy, which is a critically constrained resource. In this paper, we analyze the trade-off between power consumption and prediction accuracy of context classifiers working on dual-axis accelerometer data collected from the eWaich sensing and notification platform. We improve power consumption techniques by providing competitive classification performance even in the low frequency region of 1-10 Hz and for the highly erratic wrist based sensing location. Furthermore, we propose and analyze a collection of selective sampling strategies in order to reduce the number of required sensor readings and the computation cycles even further. Our results indicate that optimized sampling schemes can increase the deployment lifetime of a wearable computing platform by a factor of four without a significant loss in prediction accuracy.

Selective Sampling Strategies to Conserve Power in Context Aware Devices

We analyze the use of selective sampling strategies to aid in power conservation in sensor platforms for context-aware systems. In particular, we study an activity-aware system based on the eWatch sensor and notification platform, developed at CMU. We collected 94 hours of self-annotated activity data from four subjects over several days each. We compare sampling strategies according to several metrics, each of which satisfies a different set of application needs. These metrics include: accuracy as the percentage of time between samples that sampled activity matches true activity, average latency of detecting a change in activity, the percentage of missed activities, and the percentage of redundant samples. We consider both the performance differences between strategies as well as differences between subjects. Accuracies of over 95% were achievable using only 3% of the samples.

HMM-based speech enhancement using harmonic modeling

This paper describes a technique for reduction of non-stationary noise in electronic voice communication systems. Removal of noise is needed in many such systems, particularly those deployed in harsh mobile or otherwise dynamic acoustic environments. The proposed method employs state-based statistical models of both speech and noise, and is thus capable of tracking variations in noise during sustained speech. This work extends the hidden Markov model (HMM) based minimum mean square error (MMSE) estimator to incorporate a ternary voicing state, and applies it to a harmonic representation of voiced speech. Noise reduction during voiced sounds is thereby improved. Performance is evaluated using speech and noise from standard databases. The extended algorithm is demonstrated to improve speech quality as measured by informal preference tests and objective measures, to preserve speech intelligibility as measured by informal diagnostic rhyme tests, and to improve the performance of a low bit-rate speech coder and a speech recognition system when used as a pre-processor.

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS

Advanced human-machine interfaces require improved embedded sensors that can seamlessly interact with the user. Voice-based communication has emerged as a promising interface for next generation mobile, automotive and hands-free devices. Presented here is such an audio front-end with Voice Activity Detection (VAD) hardware targeted for low-power embedded SoCs, featuring a 512 pt FFT, programmable filters, noise floor estimator and a decision engine which has been fabricated in 32 nm CMOS. The dual-VCC, dual-frequency design allows the core datapath to scale to near-threshold voltage (NTV), where power consumption is less than 50 uW. At peak energy efficiency, the core can process audio data at 2.3 nJ/frame - a 9.4X improvement over nominal voltage conditions.

Novel CI-backoff scheme for real-time embedded speech recognition

A new method for reduction of computation and memory bandwidth for embedded large vocabulary continuous speech recognition is presented. During the Hidden Markov model state likelihood computation, scores for selected context-dependent (triphone) model states are computed for several frames in advance. Scores that are subsequently needed for Viterbi search but not found in the buffer are replaced by the scores for associated context independent (monophone) models. On the Wall Street Journal 20,000 word continuous speech recognition task, an overall reduction of 58% memory bandwidth and decrease of 23% execution time is achieved relative to an assembly optimized implementation of Sphinx 3. Recognition accuracy is reduced by ≪1% while recognition latency is increased by 30 milliseconds.

ISIS: An accelerator for Sphinx speech recognition

The ability to naturally interact with devices is becoming increasingly important. Speech recognition is one well-known solution to provide easy, hands-free user-device interaction. However, speech recognition has significant computation and memory bandwidth requirements, making it challenging to offer at high performance, real-time and ultra-low power for handheld devices. In this paper, we present a speech recognition accelerator called ISIS. We show the overall execution flow of the accelerated speech recognition solution along with optimizations and the key metrics of performance, area and power.

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS

An audio front-end with Voice Activity Detection (VAD) hardware targeted for low-power embedded SoCs, featuring a 512pt FFT, programmable filters, noise floor estimator and a decision engine has been fabricated in 32nm CMOS. The dual-VCC, dual-frequency design allows the core datapath to scale to near-threshold voltage, where power consumption is less than 50μW. At peak energy efficiency, the core can process audio data at 2.3nJ/frame - a 9.4X improvement over nominal voltage conditions.

Efficient second-order adaptation for large vocabulary distributed speech recognition

This paper describes practical implementation details for a second-order approximation to the parallel model combination (PMC) algorithm with application to large vocabulary distributed speech recognition. The proposed method is capable of simultaneously adapting to noise and channel changes. A more accurate method for computing the derivatives based on numeric integration PMC is introduced. The proposed second-order adaptation algorithm requires only twice the memory and computation of standard Jacobian Adaptation (JA). This represents a 382-fold reduction in memory and a 29-fold reduction in computation. Moreover, the proposed algorithm produces models that are much closer to the PMC-derived models than standard JA.