Michael Engel

Thin Film Nanotube Transistors Based on Self-Assembled, Aligned, Semiconducting Carbon Nanotube Arrays

Thin film transistors (TFTs) are now poised to revolutionize the display, sensor, and flexible electronics markets. However, there is a limited choice of channel materials compatible with low-temperature processing. This has inhibited the fabrication of high electrical performance TFTs. Single-walled carbon nanotubes (CNTs) have very high mobilities and can be solution-processed, making thin film CNT-based TFTs a natural direction for exploration. The two main challenges facing CNT-TFTs are the difficulty of placing and aligning CNTs over large areas and low on/off current ratios due to admixture of metallic nanotubes. Here, we report the self-assembly and self-alignment of CNTs from solution into micron-wide strips that form regular arrays of dense and highly aligned CNT films covering the entire chip, which is ideally suitable for device fabrication. The films are formed from pre-separated, 99% purely semiconducting CNTs and, as a result, the CNT-TFTs exhibit simultaneously high drive currents and large on/off current ratios. Moreover, they deliver strong photocurrents and are also both photo- and electroluminescent.

Origin of photoresponse in black phosphorus phototransistors

We study the origin of a photocurrent generated in doped multilayer black phosphorus (BP) phototransistors, and find that it is dominated by thermally driven thermoelectric and bolometric processes. The experimentally observed photocurrent polarities are consistent with photothermal processes. The photothermoelectric current can be generated up to a micrometer away from the contacts, indicating a long thermal decay length. With an applied source-drain bias, a photobolometric current is generated across the whole device, overwhelming the photothermoelectric contribution at a moderate bias. The photoresponsivity in the multilayer BP device is two orders of magnitude larger than that observed in graphene.

The polarized carbon nanotube thin film LED

We demonstrate a light emitting p-i-n diode made of a highly aligned film of separated (99%) semiconducting carbon nanotubes, self-assembled from solution. By using a split gate technique, we create p- and n-doped regions in the nanotube film that are separated by a micron-wide gap. We inject p- and n-type charge carriers into the device channel from opposite contacts and investigate the radiative recombination using optical micro-spectroscopy. We find that the threshold-less light generation efficiency in the intrinsic carbon nanotube film segment can be enhanced by increasing the potential drop across the junction, demonstrating the LED-principle in a carbon nanotube film for the first time. The device emits infrared light that is polarized along the long axes of the carbon nanotubes that form the aligned film.

Power Dissipation and Electrical Breakdown in Black Phosphorus

We report operating temperatures and heating coefficients measured in a multilayer black phosphorus device as a function of injected electrical power. By combining micro-Raman spectroscopy and electrical transport measurements, we have observed a linear temperature increase up to 600 K at a power dissipation rate of 0.896 K μm(3)/mW. By further increasing the bias voltage, we determined the threshold power and temperature for electrical breakdown and analyzed the fracture in the black phosphorus layer that caused the device failure by means of scanning electron microscopy and atomic force microscopy. The results will benefit the research and development of electronics and optoelectronics based on novel two-dimensional materials.

Hot spot dynamics in carbon nanotube array devices.

We report on the dynamics of spatial temperature distributions in aligned semiconducting carbon nanotube array devices with submicrometer channel lengths. By using high-resolution optical microscopy in combination with electrical transport measurements, we observe under steady state bias conditions the emergence of time-variable, local temperature maxima with dimensions below 300 nm, and temperatures above 400 K. On the basis of time domain cross-correlation analysis, we investigate how the intensity fluctuations of the thermal radiation patterns are correlated with the overall device current. The analysis reveals the interdependence of electrical current fluctuations and time-variable hot spot formation that limits the overall device performance and, ultimately, may cause device degradation. The findings have implications for the future development of carbon nanotube-based technologies.

Top-gated Thin Film FETs Fabricated from Arrays of Self-aligned Semiconducting Carbon Nanotubes

In this paper, we present a new approach for making active carbon nanotube (CNT) electrical devices and demonstrate the first aligned CNT array field effect transistors (FET) from 99% pure separated semiconducting nanotubes. Through evaporation-driven deposition of predominantly semiconducting nanotubes from the liquid phase, we have fabricated aligned, thin-film CNT devices with high on-state currents. The fabrication scheme presented here provides a versatile production method translatable to other substrates such as flexible plastics.

Graphene-enabled and directed nanomaterial placement from solution for large-scale device integration

Directed placement of solution-based nanomaterials at predefined locations with nanoscale precision limits bottom-up integration in semiconductor process technology. We report a method for electric-field-assisted placement of nanomaterials from solution by means of large-scale graphene layers featuring nanoscale deposition sites. The structured graphene layers are prepared via either transfer or synthesis on standard substrates, and then are removed once nanomaterial deposition is completed, yielding material assemblies with nanoscale resolution that cover surface areas >1u2009mm2. In order to demonstrate the broad applicability, we have assembled representative zero-dimensional, one-dimensional, and two-dimensional semiconductors at predefined substrate locations and integrated them into nanoelectronic devices. Ultimately, this method opens a route to bottom-up integration of nanomaterials for industry-scale applications.The placement of nanomaterials at predefined locations is a key requirement for their integration in nanoelectronic devices. Here, the authors devise a method allowing placement of solution-based nanomaterials by using structured graphene layers as deposition sites with the aid of an electric field.

Modeling fluid transport in 2d paper networks

Paper-based microfluidic devices offer great potential as a low-cost platform to perform chemical and biochemical tests. Commercially available formats such as dipsticks and lateral-flow test devices are widely popular as they are easy to handle and produce fast and unambiguous results. While these simple devices lack precise control over the flow to enable integration of complex functionality for multi-step processes or the ability to multiplex several tests, intense research in this area is rapidly expanding the possibilities. Modeling and simulation is increasingly more instrumental in gaining insight into the underlying physics driving the processes inside the channels, however simulation of flow in paper-based microfluidic devices has barely been explored to aid in the optimum design and prototyping of these devices for precise control of the flow. In this paper, we implement a multiphase fluid flow model through porous media for the simulation of paper imbibition of an incompressible, Newtonian fluid such as when water, urine or serum is employed. The formulation incorporates mass and momentum conservation equations under Stokes flow conditions and results in two coupled Darcy’s law equations for the pressures and saturations of the wetting and non-wetting phases, further simplified to the Richard’s equation for the saturation of the wetting fluid, which is then solved using a Finite Element solver. The model tracks the wetting fluid front as it displaces the non-wetting fluid by computing the time-dependent saturation of the wetting fluid. We apply this to the study of liquid transport in two-dimensional paper networks and validate against experimental data concerning the wetting dynamics of paper layouts of varying geometries.

Nanoscale Flow Chip Platform for Laboratory Evaluation of Enhanced Oil Recovery Materials

We present a lab-on-chip platform for the experimental evaluation of Enhanced Oil Recovery (EOR) methods from the nanoscale to the scale of reservoir rock pore networks. We have employed semiconductor process technology to build lab-on-chip flow devices with features at the nanometer scale that allow us to perform controlled flow experiments for calibrating multiscale flow models. The platform built on silicon semiconductor technology is highly customizable and allows for design adaptation of different physical model representations. The approach enables us to experimentally investigate and validate liquid flow in porous media below the micrometer scale and to deploy calibrated, multi-scale flow simulations in a digital representation of a given rock pore network. The chip implementations of the nanoscale, porous rock network enable systematic flow studies covering various parameters (e.g. effective porosity, viscosity, surface properties) under controlled conditions of physical parameters (e.g. temperature, pressure). High resolution optical microscopy measurement techniques enable us to track individual nanometer size fluorescent tags which allow us to directly determine fluid flow speeds even in sub-micrometer constrictions. We introduce the architecture of the flow chip, discuss how the flow experiments are performed and how the experimental results are used to calibrate the flow simulations. Ultimately, the calibrated flow simulations will be used for predicting the efficiency of a specific EOR agent for improving oil displacement in a pore scale network of reservoir rock.