Michael I. Ferguson

Evolving circuits in seconds: experiments with a stand-alone board-level evolvable system

The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function. SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution. It also illustrates how specifications not completely reflected in the fitness function, such as the time scales of response for logical circuits, may lead to overall unsatisfactory solutions. Both such situations can be handled with appropriate modification of fitness function and additional testing.

Evolutionary computation technologies for space systems

The Evolvable Computation Group, at NASAs Jet Propulsion Laboratory, is tasked with demonstrating the utility of computational engineering and computer optimized design for complex space systems. The group is comprised of researchers over a broad range of disciplines including biology, genetics, robotics, physics, computer science and system design, and employs biologically inspired evolutionary computational techniques to design and optimize complex systems. Over the past two years we have developed tools using genetic algorithms, simulated annealing and other optimizers to improve on human design of space systems. We have further demonstrated that the same tools used for computer-aided design and design evaluation can be used for automated innovation and design. These powerful techniques also serve to reduce redesign costs and schedules

Experimental results in evolutionary fault-recovery for field programmable analog devices

This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit digital to analog converter (DAC) using the JPL stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems and provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about 100,000 circuit evaluations. Its main components are a JPL field programmable transistor array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper describes an experiment consisting of the hierarchical evolution of a 4-bit DAC using 20 cells of the FPTA chip. Fault-recovery is demonstrated after applying stuck-at 0 faults to all switches of one particular cell, and using evolution to recover functionality. It is verified that the functionality can be recovered in less than one minute after the fault is detected while the evolutionary design of the 4-bit DAC from scratch took about 3 minutes.

Intrinsic hardware evolution for the design and reconfiguration of analog speed controllers for a DC Motor

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation field programmable transistor array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

Tuning of MEMS devices using Evolutionary Computation and Open-Loop Frequency Response

We propose a tuning method for MEMS gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation

High temperature experiments using programmable transistor array

Temperature and radiation tolerant electronics, as well as long life survivability are the key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology complements material/device advancements and increases the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip, which recovers functionality until 280/spl deg/C. We show in this paper the functionality recovery at high temperatures for a variety of circuits, including rectifiers, amplifiers and filters.

Evolutionary computation applied to the tuning of MEMS gyroscopes

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation.

Evolvable hardware techniques for on-chip automated reconfiguration of programmable devices

While complete automated design is a harder problem than computer-assisted design, automated hardware reconfiguration is an even more challenging problem, because it needs to adjust to limited resources and various factors, such as noise and parasitic capacitance, a resistance and inductance. This paper presents some experimental results of on-chip automated design and reconfiguration using evolvable hardware techniques. It describes a stand-alone board level evolvable system, and its use to demonstrate on-chip synthesis of new circuits in only a few seconds. The experiments presented here indicate a recovery capability in the case of extreme environmental conditions, such as extreme temperatures, that adversely affect electronics. Some of the difficulties of dealing with the real hardware are exposed, as well as challenges more generally related to automated evolution of complex electronic systems.

On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW. The directions of growth include Software/Hardware hybrids, electronic/non-electronic hybrids, and networked systems. The research directions proposed here are (1) evolutionary compilation of descriptions from behavioral Hardware Description languages (HDL) to structural HDL (for both the case of digital and analog/mixed signal) (2) evolutionary synthesis, i.e. converting from synthesizable HDL to circuits and (3) hardware-software partitioning (co-design) for CPU/FPGA hybrids. The results presented here illustrate evolutionary design of multi-junctional/adaptive circuits including polymorphic and reconfiguration based circuits, and evolution of optimized circuits, in particular low-voltage circuits.

Evolutionary computation technologies for the automated design of space systems

The Evolvable Computation Group, at NASAs Jet Propulsion Laboratory (JPL), is tasked with demonstrating the utility of computational engineering and computer optimized design for complex space systems. The group is comprised of researchers over a broad range of disciplines including biology, genetics, robotics, physics, computer science and system design, and employs biologically inspired evolutionary computational techniques to design and optimize complex systems. Over the past two years we have developed tools using genetic algorithms, simulated annealing and other optimizers to improve on human design of space systems. We have further demonstrated that the same tools used for computer-aided design and design evaluation can be used for automated innovation and design, and be applied to hardware in the loop such as robotic arms and MEMS micro-gyroscopes. These powerful techniques also serve to reduce redesign costs and schedules.