Michael Laisne

Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture

This paper presents a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional function-based ATPG techniques alongside an implicit framework to efficiently identify testable PDFs under the LOC scan architecture, and avoids the complex backtracking performed by structural techniques which may abort PDF classifications for path intensive designs. The effectiveness and scalability of the proposed method is demonstrated on the path intensive ISCAS 89 benchmarks

Wafer probe test cost reduction of an RF/A device by automatic testset minimization — A case study

This work presents a case study of wafer probe test cost reduction by multivariate parametric testset optimization for a production RF/A device. More than 1.5 million tested device samples across dozens lots and hundreds of parametric measurements are analyzed using a new automatic testset minimization system. Parametric test subsets are found that can be used to predict infrequent wafer probe failures. Multivariate test models are generated to justify removal of ineffective tests, screen failures with minimal test cost, and demonstrate that some frequently passing tests are safe drop candidates. The proposed method is evaluated using parametric test data from an RF/A IC currently in production, showing how to reduce test cost and uncover tradeoffs between test escapes and overkills during high volume wafer probe screening.

On zero clock skew hold time failure in scan test

This paper studies a new hold time failure mode found in deep sub-micron low power CMOS production scan testing. The root causes of failure are discovered and duplicated in simulations. Vccmin of scan chain integrity is defined and studied for the first time. Solutions for enhancing scan chain integrity are proposed.

Verification and debugging of I DDQ test of low power chips

Quiescent supply current (IDDQ) is a very effective test method for CMOS circuits. However, IDDQ vector verification and debugging may take considerable time and effort; various problems have been encountered in this process, so different tools and methodologies have been devised to address them. For pre-silicon IDDQ vector verification, a modular approach is adopted. IDDQ is estimated for each vector based on leakage libraries of cells, and cell constraints can be verified automatically. For post-silicon IDDQ vector issues, methods and analysis tools have been developed to identify the root causes. Scan cell and net value analysis will identify critical scan cells and nets, which will determine whether an IDDQ pattern passes or fails, thus revealing the source of the extra leakage. These methodologies are proven to be very successful for IDDQ vector debug and IDDQ diagnosis.

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

Non-robust tests for path delay faults (PDFs) have gained importance in industry as a high percentage of PDFs are non-robustly testable in comparison to robustly testable PDFs. In this paper we present a novel function-based method to generate test patterns for the non-robust testable PDFs under the launch-off-capture (LOC) scan architecture. In contrast to a recently proposed function-based method (Flanigan, 2007) which generates LOC tests for the robustly testable paths, the proposed approach presents a new framework which simplifies the test functions and has simpler algorithms for LOC test generation. Experimental results show that the proposed method has less space and time complexity when compared to (Flanigan, 2007), and is scalable to path intensive designs