Michael Opoku Agyeman

HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

Low power heterogeneous 3D Networks-on-Chip architectures

Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. In this paper we propose low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in total crossbar area and power efficiency of the NoC resources, respectively compared to that of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers.

Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions.

Efficient routing techniques in heterogeneous 3D Networks-on-Chip

Abstract Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs. Particularly, experimental results show that our proposed architecture significantly improves the performance up to 75% by replacing 2D static routers with adaptive 2D routers in heterogeneous 3D NoCs, while keeping the maximum clock frequency, power and energy consumption of the adaptive router nearly at the same level as the static router.

Optimised Application Specific Architecture Generation and Mapping Approach for Heterogeneous 3D Networks-on-Chip

Heterogeneous architectures have emerged to combine 2D routers and 3D routers in NoCs producing 3D NoCs with lower area and power consumption while maintaining the performance of homogeneous 3D NoCs. An efficient application mapping on heterogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance, reliability and energy consumption of NoCs. This paper presents an energy and reliability aware multi-application mapping algorithm for heterogeneous 3D NoCs. The algorithm has been evaluated and compared with existing mapping algorithms including heuristics (CastNet, Onyx and Nmap), semi-exhaustive (Branch-and-Bound) and random mapping techniques with various realistic traffic patterns. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms.

Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design

Existing wireless communication interface of Hybrid Wired-Wireless Network-on-Chip (WiNoC) has 3-dimensional free space signal radiation which has high power dissipation and drastically affects the received signal strength. In this paper, we propose a CMOS based 2-dimensional (2-D) waveguide communication fabric that is able to match the channel reliability of traditional wired NoCs as the wireless communication fabric. Our experimental results demonstrate that, the proposed communication fabric can achieve a 5dB operational bandwidth of about 60GHz around the center frequency (60GHz). Compared to existing WiNoCs, the proposed communication fabric can improve the reliability of WiNoCs with average gains of 21.4%, 13.8% and 10.6% performance efficiencies in terms of maximum sustainable load, throughput and delay, respectively.

On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures

With the ever increase in transistor density over technology scaling, energy and performance aware hybrid wireless Network-on-Chip (WiNoC) has emerged as an alternative solution to the slow conventional wireline NoC design for future System-on-Chip (SoC). However, combining wireless and wireline channels drastically reduces the total reliability of the communication fabric. Besides being lossy, existing feasible wireless solution for WiNoCs, which is in the form of millimeter wave (mm-Wave), relies on free space signal radiation which has high power dissipation with high degradation rate in the signal strength per transmission distance. Alternatively, low power wireless communication fabric in the form of surface wave has been proposed for on-chip communication. With the right design considerations, the reliability and performance benefits of the surface wave channel could be extended. In this paper, we propose a surface wave communication fabric for emerging WiNoCs that is able to match the channel reliability of traditional wireline NoCs. Here, a carefully designed transducer and commercially available thin metal conductor coated with a low cost dielectric material are employed to general surface wave signal to improve the wireless signal transmission gain. Our experimental results demonstrate that, the proposed communication fabric can achieve a 5dB operational bandwidth of about 60GHz around the center frequency (60GHz). By improving the transmission reliability of wireless layer, the proposed communication fabric can improve maximum sustainable load of NoCs by an average of 20.9% and 133.3% compared to existing WiNoCs and wireline NoCs, respectively.

Optimising Heterogeneous 3D Networks-on-Chip

The emergence of the third dimension in Network-on-Chip (NoC) design as a quest to improve the quality of service (QoS) of on-chip communication has evolved with enormous interest. However the underlying router architecture of 3D NoCs have more area footprint than 2D routers. In this paper, we investigate heterogeneous 3D NoC topologies with the focus on finding a balance between the manufacturing cost and the QoS by employing the area and performance benefits provided by 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topology. Experimental results show a negligible penalty in throughput of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers. The heterogeneity however provides superiority in area efficiency of the NoC resources.

An adaptive router architecture for heterogeneous 3D Networks-on-Chip

Three dimensional Network-on-Chip (3D NoC) is becoming increasingly popular to address the on-chip communication demands of modern multi-core systems. However, architectural framework of the 3D router uses more buffer resources than conventional 2D routers. Also, homogeneous 3D NoC topologies have more TSVs which have a costly and complex manufacturing process. To improve the performance and manufacturing cost in 3D NoCs we propose adaptive router architectures for heterogeneous and homogeneous 3D NoCs which combine both the area and performance benefits of static 2D and 3D router architectures. Experimental results show that with a negligible penalty of up to 0.4% in maximum operating frequency, we achieved performance improvement of up to 34% by replacing 2D static routers with adaptive routers in heterogeneous architectures.

On the nanocommunications at THz band in graphene-enabled Wireless Network-on-Chip

One of the main challenges towards the growing computation-intensive applications with scalable bandwidth requirement is the deployment of a dense number of on-chip cores within a chip package. To this end, this paper investigates the Wireless Network-on-Chip (WiNoC), which is enabled by graphene-based nanoantennas (GNAs) in Terahertz frequency band. We first develop a channel model between the GNAs taking into account the practical issues of the propagation medium, such as transmission frequency, operating temperature, ambient pressure, and distance between the GNAs. In the Terahertz band, not only dielectric propagation loss but also molecular absorption attenuation (MAA) caused by various molecules and their isotopologues within the chip package constitutes the signal transmission loss. We further propose an optimal power allocation to achieve the channel capacity. The proposed channel model shows that the MAA significantly degrades the performance at certain frequency ranges compared to the conventional channel model, even when the GNAs are very closely located. More specifically, at transmission frequency of 1 THz, the channel capacity of the proposed model is shown to be much lower than that of the conventional model over the whole range of temperature and ambient pressure of up to 26.8% and 25%, respectively.