Michael P Nault

Process optimization of a negative-tone CVD photoresist for 193-nm lithography applications

New photoresists and processes are required for sub 0.15 micrometers design rules and currently an important effort is on- going for single layer resists optimization at 193 nm. Top surface imaging can be an interesting alternative approach. An all dry chemical vapor deposition (CVD) process based on plasma polymerized methylsilane (PPMS) or plasma polymerized dimethylsilane (PP2MS) provides a thin conformal and photosensitive layer at 193 nm. A thin amorphous film of Si- Si bonded material is deposited using plasma enhanced chemical vapor deposition with methylsilane or dimethylsilane as the gas precursor. Upon 193 nm exposure under air, photo-induced oxidation of the CVD resist occurs, generating a latent image. The image is then developed in a chlorine-based plasma, providing a negative tone process. This mask can be used to pattern a thick organic underlayer to provide a general bilevel process. Lithographic results on both a 193 microstepper as well as a full field production stepper are presented: resolution down to 0.10 micrometers equal L/S was obtained. A preliminary comparison between PPMS and PP2MS materials is presented, including FTIR results, stability of the films in air and lithographic performance including line edge roughness.

Feasibility of a CVD-resist-based lithography process at 193-nm wavelength

Thin layer imaging can extend the optical lithography limit down to sub-0.18 micrometers CD with 193 nm wavelength tools. Thin layer imaging can be implemented in a bi-layer approach, in which a patterned thin layer is transferred into an underlying organic planarizing layer. It can also be implemented in a single-layer hardmask process, in which a photodefineable oxide precursor is used to directly pattern a device layer. In the first portion of our study, a plasma polymerized methyl silane (PPMS) bi-layer baseline process has been characterized for photospeed, resolution, and line edge roughness (LER). 1500 angstroms thick organosilane films were patterned by a photo-oxidation process using a 193 nm stepper (NA equals 0.6). The process exhibits photospeeds that are easily tuned from 40 to 100 mJ/cm2 in a well-controlled manner by adjusting the PPMS CVD deposition parameters. The process has demonstrated a resolution of 0.13 micrometers . We show that the total dry-develop process time is critical in determining the lithographic process latitude, photospeed, resolution and LER characteristics. The CVD resist process is most attractive if the thin layer can be directly converted into a thin oxide hard mask, useful for transferring the pattern directly into an underlying device layer. We demonstrate a CVD photoresist process in which patterned PPMS is converted into a silicon dioxide hardmask, and then transferred into underlying amorphous-Si layers with high sensitivity. Using this technique, we have successfully demonstrated 0.15 micrometers resolution amorphous-Si lines.

Progress of a CVD-based photoresist 193-nm lithography process

Plasma polymerized organosilane resists films have been shown to exhibit high sensitivity to DUV radiation. We have previously demonstrated a 193nm CVD photoresist process in which plasma polymerized methylsilane (PPMS) is patterned via photo-oxidation, dry-developed, converted into silicon dioxide, and then transferred into an underlying Si layer with high selectivity. The PPMS resist exhibits linearity down to a resolution of 130 nm L/S for a 1:1 pitch. We have demonstrated 100 nm Iso-lines at 28 mJ/cm2 dose with 11 percent dose latitude and 600 nm focus latitude. Depths of focus greater than 500 nm have been demonstrated for 160 nm nested L/S.

CVD photoresist processes for sub-0.18 design rules

The CVD photoresist material plasma polymerized methylsilane (PPMS) provides a thin film high resolution imaging layer for 193 nm lithography. Patterned films are readily converted into silicon dioxide hard masks useful for patterning critical device layers with high selectivity. We describe the application of this process for patterning polysilicon gates and new a low /spl kappa/ dielectric material.