Michael R. Bodnar

Floating-Point Accumulation Circuit for Matrix Applications

Many scientific algorithms require floating-point reduction operations, or accumulations, including matrix-vector-multiply (MVM), vector dot-products, and the discrete cosine transform (DCT). Because FPGA implementations of each of these algorithms are desirable, it is clear that a high-performance, floatingpoint accumulation unit is necessary. However, this type of circuit is difficult to design in an FPGA environment due to the deep pipelining of the floatingpoint arithmetic units, which is needed in order to attain high performance designs (Durbano et al., 2004, Leeser and Wang, 2004). A deep pipeline requires special handling in feedback circuits because of the long delay, which is further complicated by a continuous input data stream. Proposed accumulator architectures, which overcome such performance bottlenecks, are described in Zuo et al. (2005) and Zuo and Prassana (2005). This paper presents a floating-point accumulation circuit that is a natural evolution of this work. The system can handle streams of arbitrary length, requires modest area, and can handle interrupted data inputs. In contrast to the designs proposed by Zhuo et al., the proposed architecture maintains buffers for partial result storage which utilize significantly less embedded memory resources, while maintaining fixed size and speed characteristics, regardless of stream length. The results for both single- and double-precision accumulation architectures was verified in a Virtex-II 8000-4 part clocked at more than 150 MHz, and the power of this design was demonstrated in a computationally intense, matrix-matrix-multiply application

Real-time Embedded Atmospheric Compensation for Long-Range Imaging Using the Average Bispectrum Speckle Method

While imaging over long distances is critical to a number of security and defense applications, such as homeland security and launch tracking, current optical systems are limited in resolving power. This is largely a result of the turbulent atmosphere in the path between the region under observation and the imaging system, which can severely degrade captured imagery. There are a variety of post-processing techniques capable of recovering this obscured image information; however, the computational complexity of such approaches has prohibited real-time deployment and hampers the usability of these technologies in many scenarios. To overcome this limitation, we have designed and manufactured an embedded image processing system based on commodity hardware which can compensate for these atmospheric disturbances in real-time. Our system consists of a reformulation of the average bispectrum speckle method coupled with a high-end FPGA processing board, and employs modular I/O capable of interfacing with most common digital and analog video transport methods (composite, component, VGA, DVI, SDI, HD-SDI, etc.). By leveraging the custom, reconfigurable nature of the FPGA, we have achieved performance twenty times faster than a modern desktop PC, in a form-factor that is compact, low-power, and field-deployable.

Comparing FPGAs and GPUs for high-performance image processing applications

Modern image enhancement techniques have been shown to be effective in improving the quality of imagery. However, the computational requirements of applying such algorithms to streams of video in real-time often cannot be satisfied by standard microprocessor-based systems. While a scaled solution involving clusters of microprocessors may provide the necessary arithmetic capacity, deployment is limited to data-center scenarios. What is needed is a way to perform these techniques in real time on embedded platforms. A new paradigm of computing utilizing special-purpose commodity hardware including Field-Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPU) has recently emerged as an alternative to parallel computing using clusters of traditional CPUs. Recent research has shown that for many applications, such as image processing techniques requiring intense computations and large memory spaces, these hardware platforms significantly outperform microprocessors. Furthermore, while microprocessor technology has begun to stagnate, GPUs and FPGAs have continued to improve exponentially. FPGAs, flexible and powerful, are best targeted at embedded, low-power systems and specific applications. GPUs, cheap and readily available, are available to most users through their standard desktop machines. Additionally, as fabrication scale continues to shrink, heat and power consumption issues typically limiting GPU deployment to high-end desktop workstations are becoming less of a factor. The ability to include these devices in embedded environments opens up entire new application domains. In this paper, we investigate two state-of-the-art image processing techniques, super-resolution and the average-bispectrum speckle method, and compare FPGA and GPU implementations in terms of performance, development effort, cost, deployment options, and platform flexibility.

An embedded processor for real-time atmoshperic compensation

Imaging over long distances is crucial to a number of defense and security applications, such as homeland security and launch tracking. However, the image quality obtained from current long-range optical systems can be severely degraded by the turbulent atmosphere in the path between the region under observation and the imager. While this obscured image information can be recovered using post-processing techniques, the computational complexity of such approaches has prohibited deployment in real-time scenarios. To overcome this limitation, we have coupled a state-of-the-art atmospheric compensation algorithm, the average-bispectrum speckle method, with a powerful FPGA-based embedded processing board. The end result is a light-weight, lower-power image processing system that improves the quality of long-range imagery in real-time, and uses modular video I/O to provide a flexible interface to most common digital and analog video transport methods. By leveraging the custom, reconfigurable nature of the FPGA, a 20x speed increase over a modern desktop PC was achieved in a form-factor that is compact, low-power, and field-deployable.

Hardware acceleration of the motion compensation algorithms in synthetic aperture radar (SAR) platforms

Synthetic Aperture Radar (SAR) techniques employ radar waves to generate high-resolution images in all illumination/weather conditions. The onboard implementation of the image reconstruction algorithms allows for the transmission of real-time video feeds, rather than raw radar data, from unmanned aerial vehicles (UAVs), saving significant communication bandwidth. This in turn saves power, enables longer missions, and allows the transmission of more useful information to the ground. For this application, we created a hardware architecture for a portable implementation of the motion compensation algorithms, which are more computationally intensive than the SAR reconstruction itself, and without which the quality of the SAR images is severely degraded, rendering them unusable.

Adaptive grating interferometric sensor for NDE metrology in high energy electromagnetic environment

CCD cameras and CMOS devices are the major electronic components of industrial metrology, which are vulnerable to high level electromagnetic exposure. Typical sources of exposure of electronics to ionizing radiation are the Van Allen radiation belts for satellites, nuclear reactors in power plants for sensors and control circuits, particle accelerators for control electronics particularly particle detector devices, residual radiation from isotopes in chip packaging materials, cosmic radiation for spacecraft and highaltitude aircraft, and nuclear explosions for potentially all military and civilian electronics. A total dose 5 ×103 rad was delivered to silicon-based devices in seconds to minutes caused long-term degradation. We demonstrated adaptive grating, 3D image sensor for NDE metrology which is non vulnerable for high level X-Ray1 and 3 × 106 rad gamma radiation exposure. Sensor is based on adaptive holographic grating generated by 632.8 nm He-Ne laser - in doped electro optic Bismuth Titanate (BTO) monocrystal. Mathematical algorithm of bipolar model conductivity in BTO crystal has been applied for experimental analyses. Applications of proposed sensor for airspace, military, nuclear and civil engineering industries have been discussed.

Accelerated determination of UAV flight envelopes

Unmanned Aerial Vehicle (UAV) system integration with naval vessels is currently realized in limited form. The operational envelopes of these vehicles are constricted due to the complexities involved with at-sea flight testing. Furthermore, the unsteady nature of ship airwakes and the use of automated UAV control software necessitates that these tests be extremely conservative in nature. Modeling and simulation are natural alternatives to flight testing; however, a fully-coupled computational fluid dynamics (CFD) solution requires many thousands of CPU hours. We therefore seek to decrease simulation time by accelerating the underlying computations using state-of-the-art, commodity hardware. In this paper we present the progress of our proposed solution, harnessing the computational power of high-end commodity graphics processing units (GPUs) to create an accelerated Euler equations solver on unstructured hexahedral grids.

Multiple hardware-acceleration platforms for the full-wave analysis of circuits

Multiple hardware-acceleration platforms for the full-wave analysis of circuits was presented in this paper. The authors seek to alleviate the well-known computational bottleneck of the Arnoldi-based iterative kernels, such as conjugate gradients (CG) and generalized minimal residuals (GMRES), in an effort to provide tremendous performance gains compared to the respective software implementation. The matrix-vector product operation required at each iteration in the construction of the Krylov subspace, which is the main bottleneck, is the target operation for these acceleration platforms.

Introduction to CEMPACK: A Benchmarking System for Computational Electromagnetic Solvers

This paper introduces a computational electromagnetic (CEM)-solver benchmarking suite, called CEMPACK. CEMPACK consists of several synthetic benchmark problems that can be used to characterize CEM-solver implementations. The problems are synthetic in that they do not necessarily correspond to physically useful problems or scenarios. Rather, they attempt to stress various aspects of a solver implementation, including maximum problem size, absorbing boundary conditions, and various source types

Reconfigurable architecture for the efficient solution of large-scale non-Hermitian eigenvalue problems

The solution of large eigensystems has numerous applications in engineering and science, including circuit simulation, mechanical structure stability, and quantum physics. In particular, many optics and photonics applications, such as the design of photonic crystal slab devices, dispersion engineering, and other iterative-based design techniques, require an eigenvalue solver. Unfortunately, brute force solutions exhibit a computational complexity of O(n3), rendering them entirely impractical for medium to large matrices. Although techniques have been developed to reduce this complexity to O(n2), these algorithms are restricted to special cases such as real, symmetric, or sparse matrices, limiting the applicability of these solutions. Thus, there is a clear need for a high-performance eigenvalue solver for large, non-hermitian matrices. To this end, we are developing a novel, hardware-based platform for the analysis of eigenvalue problems. In this paper, we describe this platform and its application to eigenvalue problems, as well as our progress to date.